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authorHsuan-ting Chen <roccochen@google.com>2021-10-27 10:59:41 +0000
committerFelix Held <felix-coreboot@felixheld.de>2021-11-15 12:00:12 +0000
commit642508aa9c44daaad6963df76630d0271cf0930e (patch)
tree48fc09455e47c1e09566a73931c96f8a1a45707b /src/mainboard/google/poppy/variants
parent436eac827aea4839169f2421006df42b8c5c379f (diff)
Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/nami/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/rammus/gpio.c3
-rw-r--r--src/mainboard/google/poppy/variants/soraka/gpio.c4
7 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c
index d3ea6b537b..ffea694910 100644
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -345,6 +345,9 @@ static const struct pad_config early_gpio_table[] = {
/* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c
index d3df99e44f..ea9de7aa54 100644
--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c
+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c
@@ -341,6 +341,9 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 6dba783920..b5ec95405e 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -346,6 +346,9 @@ static const struct pad_config early_gpio_table[] = {
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c
index 37378f93a7..e06355a3b7 100644
--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c
+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c
@@ -331,6 +331,9 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index f5344584ba..6324d8fa47 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -352,6 +352,9 @@ static const struct pad_config early_gpio_table[] = {
/* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */
PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c
index 8e9e5c01c5..c67c560c70 100644
--- a/src/mainboard/google/poppy/variants/rammus/gpio.c
+++ b/src/mainboard/google/poppy/variants/rammus/gpio.c
@@ -349,6 +349,9 @@ static const struct pad_config early_gpio_table[] = {
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index 9d52773271..808ab3b504 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -342,6 +342,10 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, RSMRST),
+
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP),
+
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */