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This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:79617938
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", flash nocturne,
boot to kernel, run evtest and verify that cros-ec-buttons is present
and functional.
Change-Id: Id710782e1f4e18eaac2a90c7c0f91af5223dbce3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable I2C #5 for rear camera and SAR.
BUG=b:79784124
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5
is detected.
Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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- add ACPI register information for touchscreen WCOM digitizer
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify
touchscreen on Nocturne board works.
Change-Id: I9790a930e8ed2748d568ce58c931ce34b3e22007
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify pogo
pin port is working.
Change-Id: Ide7359366821f33c4746284e65cacdf4e240931d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new variant of poppy for the nocturne board.
Key differences from baseboard include:
- GPIO changes
- devicetree.cb changes
- memory stuffing option changes
BUG=b:78122599
BRANCH=none
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I11c7829041b3c45407c17f71b08cc7fc17f717e8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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