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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/nyan_big: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie6fb3a47a6ac39a435605ef6aeb30f8001c0a166 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-07nyan: Avoid running early_mainboard_init twice in vboot contextPaul Kocialkowski
A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-06-30google/nyan: remove timestamp leftovers from upstreamingPatrick Georgi
Initializing timestamps and writing the "start romstage" timestamp already happens earlier. One question to sort out is what to do about the migration into cbmem, but at least this compiles again. Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-11chromeos: remove vboot_verify_firmware()Aaron Durbin
vboot_verify_firmware() was only defined to ease upstreaming. It was only an empty inline as it is so remove it. Additionally, vboot2 does not require romstage_handoff so there's no need in adding it for the nyan boards. Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-08tegra124: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra124 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze. Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88 Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224504 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
The existing cpu_reset does board-wide reset, thus, should be renamed. BUG=none BRANCH=none TEST=Built firmware for Nyans. Ran faft on Blaze. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9 Original-Reviewed-on: https://chromium-review.googlesource.com/212982 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f Reviewed-on: http://review.coreboot.org/9179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-24vboot2: separate verstage from bootblockDaisuke Nojiri
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24nyans: reduce code duplication in bootblock and romstagesDaisuke Nojiri
this change reduces the code duplication of the bootblock and the romstages for Nyans. BUG=none TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri) Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a Original-Reviewed-on: https://chromium-review.googlesource.com/214050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef Reviewed-on: http://review.coreboot.org/8880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20romstages: use common run_ramstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_ramstage() to perform the necessary work to load and run ramstage. Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13nyan: Remove broken setup_display() from romstageJulius Werner
This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc Reviewed-on: http://review.coreboot.org/8638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-10ARM romstages: Support and fix COLLECT_TIMESTAMPSKyösti Mälkki
Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8021 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-12-26nyan*: Detect watchdog resets and reset the whole machine.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. That puts the machine in a funny state and may prevent it from booting properly. BUG=chrome-os-partner:28559 TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/198582 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7900 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17nyan*: cbmem: Move the call to cbmemc_reinit.Gabe Black
The call was after the call to vboot_verify_firmware and so would only be called when falling back to RO, aka recovery mode. This change moves it to before vboot_verify_firmware so we'll always have the cbmem console. BUG=None TEST=Built and booted on nyan and verified that the cbmem console was the same as the serial output. Built for big and blaze. BRANCH=nyan Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196158 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5 Reviewed-on: http://review.coreboot.org/7777 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: pinmux: fix PWM1/2 conflictsTom Warren
GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO. Even though no problems were caused by this, correct it here so we get a conflict-free pinmux map. BUG=chrome-os-partner:27091 BRANCH=none TEST=Built and booted on Nyan, ran TegraShell "pinmux check" and saw no conflicts. Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194582 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c Reviewed-on: http://review.coreboot.org/7759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
This change takes about 8K of space away from the cbfs cache and repurposes it for the cbmem console buffer. This is a little more than twice the space we currently need for the bootblock and ROM stage to give us some room to grow and for extra debug output if needed. BUG=None TEST=Built and booted on nyan. Checked the cbmem output. BRANCH=None Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193169 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab Reviewed-on: http://review.coreboot.org/7757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyans: prepare for vboot verification of ramstageAaron Durbin
Set the appropriate config options and make the appropriate calls to perform vboot verification. The flashmap offset as well as the TPM information needs to be properly set. Lastly, call into vboot_verify_firmware() to perform the vboot verification when it is enabled. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vboot verification on nyan. Original-Change-Id: I6113badd6143008ceb2b80f0ec0832e1addd03d7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/190928 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8c6c48c7823738bf9b029a467b077d2ee20d04e5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a442b1b0fff55e737df2e96740c05c1726502d5 Reviewed-on: http://review.coreboot.org/7743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: Reduce the EC SPI bus frequency to 3 MHz.Gabe Black
The EC doesn't seem to be able to handle its bus running at 4 MHz or higher. To avoid it not being able to keep up, we reduce the frequency of that bus on all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we switch the clock source to CLKM. BUG=chrome-os-partner:22849 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I8f31b41098d64634427b4686f5333012f643fada Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193349 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c215c50a5bb982b0e671c951e2fe8df06db85db2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia60513d118aed8881927e9d52f170e27655ea8e7 Reviewed-on: http://review.coreboot.org/7739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-14nyan: tpm: Increase the TPM frequency to 400 KHz.Gabe Black
The TPM now works correctly with the I2C bus running at 400 KHz. Running it at that frequency saves some boot time. CQ-DEPEND=CL:191634 CQ-DEPEND=CL:191793 BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with and without EFS. BRANCH=None Original-Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191813 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 39a740d488d8f33ee698805bc2a8438263162cc8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I02978407e20cc9d526545157a3a3304729a91010 Reviewed-on: http://review.coreboot.org/7461 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14nyan: Move some pinmux and clock/reset configuration to ROM stage.Gabe Black
To enable EFS, we need to be able to talk to the TPM and the EC before the RAM stage starts. That means we need to set up the pins for those busses, clock those controllers and take them out of reset. BUG=None TEST=Built for nyan, nyan_big, and nyan_blaze. Booted on nyan. With other changes which implement EFS on nyan, saw EC and TPM communication work when in vboot. BRANCH=None Original-Change-Id: Ic65d69fd42beec5f03084c8cb970927c2f69dfb6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191390 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d9c176536b1e2eba47fdca90dd3346052573223e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id3117bd0c36f8b92d85cc0cefde2bed9d8de90d0 Reviewed-on: http://review.coreboot.org/7456 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: nyan_big: Mark the address range covering the SRAM as cachable.Gabe Black
The SRAM is very likely faster than going all the way out to DRAM for data, but I don't think it's part of the cores themselves and won't be as fast as the L1 caches. Enabling caching for this region reduces the time it takes to get to the payload by about 75% when serial output is disabled and the main part of display init is commented out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188459 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e Reviewed-on: http://review.coreboot.org/7407 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Check dram_end when setting up caching in ROM stage.Gabe Black
When setting up caching on nyan and big, we would set the region after DRAM to the end of the address space as uncachable. DRAM may actually extend beyond the end of the address space, so that may result in address aliasing or other problems. This change adds a check to make sure there's actually space there. BUG=None TEST=Built for big. BRANCH=None Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186769 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5 Reviewed-on: http://review.coreboot.org/7405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
We'd been putting some data structures like the framebuffer and the cbmem at the end of memory, but that may not actually be addressable as identity mapped memory. This change clamps the addresses those structures are placed at so they stay below 4GB. BUG=None TEST=Booted on nyan. Went into recovery mode and verified that there was a recovery screen. Forced memory size to be 4GB and verified that the recovery screen still shows up. BRANCH=None Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185571 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615 Reviewed-on: http://review.coreboot.org/7397 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-12nyan: Use asm volatile instead of plain asm so it doesn't get optimized out.Gabe Black
If an asm blob isn't marked as volatile, gcc is free to throw it out if it doesn't think it produces any values that are actually used. To prevent that from happening, add volatile to some asm blobs in the nyan romstage code. BUG=None TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: I819e068e738e94ea749fcb72bba2eee080e1dfb1 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 76c09581d6ca4dc6c2f9048f599822939f439d11) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0b32197abf0ddc5f454f9c2415a65d98c60ca48b Reviewed-on: http://review.coreboot.org/7396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-22tegra/nyan*: sdram updatesTom Warren
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-09-24big: Create a nyan_big mainboard which is a copy of nyan.Gabe Black
The nyan_big mainboard is very similar to nyan, but will be different in a few ways. For instance, the BCT will be different, and the GPIOs may need to be configured slightly differently. This change also adds prefixes to the kconfig variables in "choice" blocks for both boards since having multiple instances of choice blocks with the same options confuses kconfig even if all of the instances have mutually exclusive dependencies. Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183532 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6927 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 20:03:30 +0000