coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-11-12	soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree	Arthur Heymans
2022-08-14	broadwell: Move some MRC/refcode settings to devicetree	Angel Pons
2022-01-04	sb/intel: Use `bool` for PCIe coalescing option	Angel Pons
2021-01-24	mb/google/jecht: Use Haswell CPU code	Angel Pons
2020-10-30	soc/intel/broadwell: Separate PCH in devicetree	Angel Pons
2020-10-30	mb/google/jecht: Prepare devicetree for PCH split	Angel Pons
2020-07-28	broadwell: Factor out PIRQ routing from devicetree	Angel Pons
2020-07-26	mb///devicetree.cb: Normalize disabled PIRQ values	Angel Pons
2020-01-07	mb/google/{beltino,jecht}: Drop SIO configuration lines	Nico Huber
2018-08-01	mb/google,samsung/*: Add LPC TPM chip driver to devicetree	Matt DeVillier
2016-12-22	Combine Broadwell Chromeboxes using variant board scheme	Matt DeVillier
2015-06-09	google/jecht: add new mainboard	Patrick Georgi