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path: root/src/mainboard/google/hatch/variants
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2020-12-11hatch: enable genesis PCIe/USB devicesJoe Tessler
Updates PCIe registers and GPIO CLKREQ lines to match the schematic. BUG=b:173566597,b:173567124,b:173566890 TEST=build AP firmware; flash device BRANCH=none Change-Id: Ibf519b812022839f749e503436f097d3b48c4383 Signed-off-by: Joe Tessler <jrt@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08soc/intel/cannonlake: Align SATA mode names with soc/sklFelix Singer
Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-05mb/google/puff/var/dooly: Update DPTF parametersTony Huang
DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W. BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team. Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-11-22mb/google/puff/var/dooly: update USB2 type-c strengthTony Huang
Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-11-18mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplementedMatt Ziegelbaum
Ambassador is similar to puff. This change matches the PcieRpSlotImplemented configuration with Puff's, originally made for Puff in https://review.coreboot.org/c/coreboot/+/39986. Signed-off-by: Matt Ziegelbaum <ziegs@google.com> Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-18mb/google/hatch/var/ambassador: update fan table and tdp configMatt Ziegelbaum
Fan table: provided by the ODM (see attachment in bug) based on measurements with EVT unit. BUG=b:173134210 TEST=flash to DUT Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5 Signed-off-by: Matt Ziegelbaum <ziegs@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-17src: Add missing 'include <console/console.h>'Elyes HAOUAS
"printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16mb/google/hatch/dratini: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and gpio. BUG=b:172807539 Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47362 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/cnl: replace the remains of HeciEnabled by device state in dtMichael Niewöhner
The option `HeciEnabled` was partly replaced by use of the device on/off state in the devicetree in commit 3de90d1. The option has been removed from the corresponding boards, so `HeciEnabled` is always 0 and ME always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM` is set. Replace the option in the finalize function by the same dt state check that sets the FSP option and drop the remaints of `HeciEnabled`. Devicetrees still having `HeciEnabled` have been adapted to keep the current behaviour. Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/hatch: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-10mb/google/puff/var/dooly: Add WEIDA touchscreen deviceTony Huang
Adds ACPI properties for WDT8762A device. Per spec v0.8 HID name WDHT2002 T14=100ms BUG=b:163561649 BRANCH=puff TEST=emerge-puff coreboot and check system dmesg and evtest can get device. Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09hatch: Create genesis variantMatt Ziegelbaum
Create the genesis variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172620124 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_GENESIS Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09mb/google/hatch/jinlon: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and gpio. BUG=b:169840271 Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09mb/google/puff/var/dooly: Set default I2C0 frequencyTony Huang
This setting copy from puff reference board and should measure again after whole system build. BUG=b:155261464 BRANCH=puff TEST=emerge-puff coreboot and check system speaker has sound output. Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-29hatch: Create ambassador variantMatt Ziegelbaum
Create the ambassador variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171561514 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_AMBASSADOR Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28mb/google/nightfury: Set internal pull-down for GPP_D19Seunghwan Kim
Add internal pull-down for GPP_D19 to improve DMIC noise issue on nightfury. BUG=b:171669255 BRANCH=firmware-hatch-12672.B TEST=Built and checked GPP_D19 voltage after booting Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-14mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)Tony Huang
Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/google/puff/var/dooly: Update devicetree for audio and display configurationTony Huang
1. Add speaker amplifier ALC1015 2. Enable dmic+ssp registers for speaker and camera DMIC 3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree to remove unused devicesTony Huang
Remove unused device in Dooly no SD card reader no built-in LAN BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree for USB configurationTony Huang
Dooly has USBA*2 and USBC*2 BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update GPIO table for project changeTony Huang
Override unused device SD card reader, built-in LAN ALC1015 speaker amplifier SPK_AMP_ON Update touchscreen/lvds gpio pin BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-12mb/google/puff: Enable SATA0 on wyvernSam McNally
A SATA drive may be connected to SATA0. BUG=b:162909831 BRANCH=puff TEST=none Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-30mb/google/puff: Update DPTF parameters for faffyDavid Wu
1. TSRO trip point from 75C change to 73C 2. Sample period time from 5s change to 60s BUG=b:160385395 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-09mb/google/puff: Increase DPTF parameters for faffyDavid Wu
Update critical and passive policy for TSR0. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08src/mb/google/hatch: remove "sushi" variant.Paul Fagerburg
Sushi is not a real product, just a test of the new_variant program. The effort to keep it up-to-date with the rest of Hatch is no longer worth it. Remove the variant. BUG=b:168030592 TEST=build bot is successful, hatch-cq builds successfully Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08hatch: Create dooly variantTony Huang
Create the dooly variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:155261464 BRANCH=puff TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_DOOLY Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-02mb/google/puff/var/noibat: Update DPTF parameters for noibatWisley Chen
1. Update paramerters form thermal team. 2. Update PL2 Max/Min to 51W/15W. BUG=b:167494420 BRANCH=puff TEST=build noibat and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/puff: Update DPTF parameters and TCC offset for faffyDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-01mb/google/puff: Update DPTF parameters for kaisa and duffyDavid Wu
1. Apply the DPTF parameters receive from the thermal team. 2. Change PL2 min value from 25W to 15W. 3. Change PL2 max value from 64W to 51W. BUG=b:166696500 BRANCH=puff TEST=build and verify by thermal team Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01mb/google/puff: Convert ASL file to new DPTF dt implEdward O'Callaghan
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check. Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31mb/google/puff: Set TCC offset to 5 for kaisa and duffyDavid Wu
Set tcc offset to 5 degree celsius for kaisa and duffy BUG=b:166696500 BRANCH=puff TEST=Build, and verify test result by thermal team. Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27mb/google/puff: Update psyspl2 to 97% of adapter ratingDavid Wu
Set psyspl2 to 97% of adapter rating, based on our experiment results. BUG=b:160676773 TEST=Built and check firmware log. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-06mainboard/google/puff: Remove second temp sensorAndrew McRae
Newer boards have removed the second temperature sensor and relocated the remaining sensor. BUG=b:162909373 TEST=Confirm on hardware. Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-27mb/google/hatch: Add smart battery I2C passthrough for DratiniTim Wawrzynczak
Some smart battery patches have been backported to the ChromeOS 4.19 kernel, and userspace can now access smart battery data from sysfs instead of using the hacky ectool instead. Also change all space indents into tab indents while we're here. BUG=chromium:1047277 TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-14mb/hatch: Fix Puff baseboard missing mainboard symbolsEdward O'Callaghan
Fix a missing CONFIG_ prefix in Makefile. BUG=b:161154280 BRANCH=puff TEST=builds Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11 Spotted-by: Ryan Lin. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratiniWisley Chen
Screen flickered on VT2 on some devices after idle a period of time. Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking issue disappeared, and didn't affect acoustic noise much. Because CB:38212 (commit eae254e) caused this issue. BUG=b:160754994 TEST=build dratini, observe that screen flick issue disapppered Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in WyvernEdward O'Callaghan
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in NoibatEdward O'Callaghan
BUG=b:160296662 BRANCH=none TEST=none Change-Id: I5298e1779461995a98722099b397692351767089 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in FaffyEdward O'Callaghan
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in KaisaEdward O'Callaghan
BUG=b:160296661 BRANCH=none TEST=none Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in DuffyEdward O'Callaghan
BUG=b:160296325 BRANCH=none TEST=none Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/faffy: update DPTF parametersTim Chen
Modify DPTF parameters for faffy from thermal team. BUG=b:160292247 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage verify the parameters are correct Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-01mb/google/nightfury: Override VBT selection for nightfury 2nd skuSeunghwan Kim
Override VBT for nightfury SKU_ID = 2 to support different panel. BUG=b:159051021 BRANCH=firmware-hatch-12672.B TEST=Built and verified using different VBT by SKU_ID Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dtEdward O'Callaghan
BUG=b:159187889 BRANCH=none TEST=none Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-28mb/google/faffy: Enable USB2 port6Tim Chen
Due to faffy has PL-2303 connect to USB2 port6(count from port0), needs to enable it. BUG=b:159760559 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-28gpio_keys: Allow boards to configure different wakeup routesFurquan Shaikh
This change allows mainboard to configure different wakeup routes that can be used by a GPIO key: 1. SCI: This is selected when SCI route is used to wake the system. It results in _PRW property being exposed in ACPI tables. 2. GPIO IRQ: This is selected when GPIO controller wake is used to wake the system. It is typically used when the input signal is not dual routed and the GPIO controller block is not capable of applying filters for IRQ and wake separately. In this case, _PRW is not exposed in ACPI tables for the key device. 3. Disabled: No wakeup supported. Based on these wakeup routes, gpio_keys_add_child_node() is updated to expose _PRW and _DSD properties for wakeup appropriately. Additionally, the change updates mainboards that were already using gpio_keys to set wakeup_route attribute correctly and renames "wake" to "wake_gpe" to make the usage clear. BUG=b:159942427 Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-26Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"Shelley Chen
This reverts commit 1408798637125f1707ded7215e22461c623a79a8. Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause. BUG=b:159370566 BRANCH=None TEST=boot up device and make sure when kernel is booted, backlight comes up. Change-Id: I643854c6c805d262539bbb482808e8c322059a49 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-26mb/google/hatch: Set Reset Power Cycle Duration for hatch platformsSridhar Siricilla
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay. Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0 With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0 Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s. Test=Verified on Hatch and Puff boards BUG=b:158634281 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create wyvern variantPaul Fagerburg
Create the wyvern variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158269582 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_WYVERN Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create faffy variantEdward O'Callaghan
Create the faffy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). V.2: Manually modified to keep Kconfig sorted. BUG=b:157448038 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_FAFFY Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23palkia: separate the gpio pins control for the second touchZhuohao Lee
There are two touch screen controllers on the Palkia device. One is on the lid; another is on the base. To support the different control path (for example: turning off the base's touch event when we don't want to use it however still keeping the lid's touch event), we use the different gpio pins to control the second touch. As a result, we need to modify the devicetree to adopt this change. With this change, we can control the primary and secondary touch screen controller respectively. BUG=b:149714955 TEST=lid/base touch screen works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23mb/google/hatch: Make puff and variants share common mainboard.cEdward O'Callaghan
Here we consolidate some of the mainboard.c duplication between Puff and it's variants. Customizations can be done later via introducing a devicetree parameterisation. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Make puff and variants share common dptf.aslEdward O'Callaghan
Here we consolidate some of the dptf.asl duplication between Puff and it's variants. Customizations can be done later either as a direct copy or preferably via introducing a #define. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-22mb/google/hatch: Make puff and variants share common ec.hEdward O'Callaghan
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-17mb/google/hatch: mushu: Add F75303 temp sensor to dptfPuthikorn Voravootivat
Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/puff: add MST and LSPCON details to variants devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices on kaisa, duffy and noibat. BRANCH=None BUG=b:156546414 TEST=None Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/puff: add MST and LSPCON details to devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices. BRANCH=None BUG=b:156546414 TEST=Manual tested and able to see update on sysfs and ssdt table Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Tim Chen
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/hatch: Switch USB2 port1 and port3 on NoibatEdward O'Callaghan
Switch USB2 port1 and port3 for noibat due to circuit change. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I711038624f3efe397be73c29a940b3e17802598f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/hatch: Remove unused USB2 port from NoibatEdward O'Callaghan
This port isn't packed on the board, so remove from the devicetree. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/puff: Update i2c[2] and i2c[3] rise and fall timesSam McNally
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-09mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Gaggery Tsai
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-01mb/google/hatch: Add Noibat variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-26mb/google/nightfury: Enable max98390 ampSeunghwan Kim
This change enables max98390 audio codec on nightfury. BUG=b:149443429 BRANCH=firmware-hatch-12672.B TEST=Built and checked audio function on nightfury Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ic9678583370cf5e41c87e35ba12f86572708fada Reviewed-on: https://review.coreboot.org/c/coreboot/+/41127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26Mushu: Enable PCIe 1d.4 to enable dgpuShelley Chen
BUG=b:147249494,b:147249494 BRANCH=None TEST=boot up mushu check cbmem -1 to make sure PCIe 1d.4 is enabled Change-Id: I36404217f0ecffb0cce1105e76f507c9062df053 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26cannonlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26intel/cannonlake: Implement PCIe RP devicetree updateNico Huber
Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18mb/google/hatch: Add Mushu variant specific DPTF parametersJohn Su
The change applies the DPTF parameters received from thermal team. 1. Set PL1 Max to 25W 2. Set PL2 Max to 44W 3. Update Temp sensor parameters BUG=b:152011093 BRANCH=none TEST=build and verified by thermal team Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I225897832b02f9de6221053b68fbdba30f8b199a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41165 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01mb/google/hatch/vr/puff: Add psys_pmax calculationTim Chen
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-01Helios: Update DPTF settings for smooth fan speed controlSumeet R Pawnikar
Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01mb/google/nightfury: Tune the usb2_port[0] strengthSeunghwan Kim
Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-30mb/google/puff: update USB2 strengthTim Chen
Based on USB SI report to fine tune the strength for USB2 port0. BRANCH=none BUG=b:153590143 TEST=build and test USB2 port0 function works fine. Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-27mb/google/hatch/var/jinlon: Update DPTF parametersWisley Chen
The change applies the DPTF parameters received from the thermal team. 1. Set PL1 Min to 3W 2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec 3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points for tablet mode. 4. Update trigger points of CPU/TSR0/TSR1 BUG=b:154564062, b:154290855 BRANCH=hatch TEST=build and verified by thermal team. Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-25mb/google/hatch/var/jinlon: Tune i2c frequency under 400 KHzWisley Chen
Tuning i2c frequency for jinlon: I2C0: 392.7 KHz I2C1: 390 KHz I2C3: unused I2C4: 388.8 KHz BUG=b:154900217 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage, and measured with scope Change-Id: I9b186193f34027d03dd349cf1e29bb266b167383 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-24mb/google/hatch: Change baseboard EC wake & SCI masks to match kohakuTim Wawrzynczak
1) Allows MKBP events from the EC to wake the system from suspend states. 2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:148976961 BRANCH=firmware-hatch-12672.B TEST=Verify MKBP events wake system TEST=Verify MKBP IRQs are run Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-04-24mb/google/hatch: Add Duffy variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: Ic619826205be06f30055fbbc537f3d302dd039bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40423 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24mb/google/hatch: Add Kaisa variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: I7270db1283a9c0ee4746da038020e432aeb6dc5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40422 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/puff: Switch USB2 port1 and port3Tim Chen
Switch USB2 port1 and port3 for duffy and kaisa due to circuit change. BUG=b:153682207, b:154451230, b:154445635 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-04-22mb/google/puff: comment schematics changes for USBKangheui Won
USB routing has changed on reference schematics after Puff rev1 has built. This may confuse people trying to c&p devicetree from the Puff. So add comment to clearly note that there was change, hopefully preventing c&p errors. BUG=b:153682207 BRANCH=None TEST=None Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-21mb/google/puff: configure USB PLD groupsPeter Marheine
Each physical port should have the same group and position for both USB2 and USB3, but puff and its variants use different layout than the baseboard so they must override PLD. Ports are split into two groups for front and back, with positions in each group numbered from left to right. BUG=b:151579409 BRANCH=none TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT. Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20security/vboot, mb/google: Fix build errorsPatrick Georgi
There have been two cases of incompatibilities between overlapping changes, and they need to be resolved in a single commit to unbreak the tree: 1. CB:40389 introduced a new use of write_secdata while CB:40359 removed that function in favor of safe_write. Follow the refactor of the latter in the code introduced by the former. 2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface and adapted all its users. Except for duffy and kaisa which were only added in CB:40223 and CB:40393 respectively, so reapply the patch to puff's mainboard.c to their mainboard.c files. Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 21:21:55 +0000