diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-14 10:43:20 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-27 15:39:38 +0000 |
| commit | 1e5edb48c3dc66ef73a43413a27baff5a43ef268 (patch) | |
| tree | c57e009e943d1b1dc3b576ced0f20df6fc98d8d0 /src/mainboard/google/hatch/variants | |
| parent | 12baa811f0152667894c1cad8086bd6c7df318c3 (diff) | |
mb/google/hatch: Add smart battery I2C passthrough for Dratini
Some smart battery patches have been backported to the ChromeOS 4.19 kernel,
and userspace can now access smart battery data from sysfs instead of using
the hacky ectool instead.
Also change all space indents into tab indents while we're here.
BUG=chromium:1047277
TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants')
| -rw-r--r-- | src/mainboard/google/hatch/variants/dratini/overridetree.cb | 49 |
1 files changed, 34 insertions, 15 deletions
diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 2bfcc26c89..c5e2aeb2bd 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -29,16 +29,16 @@ chip soc/intel/cannonlake # Intel Common SoC Config #+-------------------+---------------------------+ - #| Field | Value | + #| Field | Value | #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | FP MCU | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -47,18 +47,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 50, - .fall_time_ns = 15, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 25, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" @@ -169,6 +169,25 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "5" + device generic 0 on + chip drivers/i2c/generic + register "hid" = ""ACPI_DT_NAMESPACE_HID"" + register "name" = ""SBS0"" + register "uid" = "1" + register "compat_string" = ""sbs,sbs-battery"" + device i2c 0b on end + end + end + end + end + end + end # eSPI Interface device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" |