Age | Commit message (Collapse) | Author |
|
The stryke project/mainboard never ended up being built and was
cancelled early on, therefore remove it from the tree.
Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Add VBTs for all hatch variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous
I2C configuration copied from Puff.
BUG=b:202195805
TEST=Boot scout, verify no more errors due to missing I2C devices
Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
No need for dynamic config (and the additional RAM training time)
on a Chromebox; always use high power/high performance mode.
Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Update the DPTF parameters received from the thermal team.
BUG=b:188596619
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The moonbuggy pcie topology is the same as genesis so copy from its
device tree and gpios in order to enable these devices.
BUG=b:199746414
TEST=lspci
Change-Id: I4e916a95047b9f955734f164d7578c520478f5af
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change replaces the device tree walks with device pointers by
adding alias for igpu (integrated graphics) device in the tree.
Change-Id: I6d159f6dc674f4a0b38ebb553c5141105405a883
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
This documentation doesn't add any more value. Thus, remove it.
Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Create the moonbuggy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=191356135
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_MOONBUGGY
Signed-off-by: Rehan Ghori <rehang@google.com>
Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
update the DPTF parameters received from the thermal team.
BUG=b:195602767
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Scout-specific changes to puff reference following bring-up
- copy baseline changes from genesis
- update GPIOs
- update PCIe ports for TPUs
- remove LSPCON
- enable eMMC
- disable touch I2C
- enable uart
BUG=b:187078663
TEST=boot scout
BRANCH=none
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
An error in script did not set the attribute properly:
- Entry CS0 is not used as sensor, but as ground,
- Entry CS1 is used as the startup sensor.
This fixes a regression caused by commit
689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names)
EQ=b:173341604
BRANCH=volteer
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the scout variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:187080143
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SCOUT
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I3be9d2d30821c2c9132ed94c9faf1f33b62bbc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
BUG=b:189053502
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: Ic2337b9eabef158633c5e6dfa935ed5c8d3d76d1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54718
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
UI monitors this input event and sends global mic mute command to CRAS
when the physical switch is toggled.
BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on DUT.
Apply crrev.com/c/2870806 with chrome cmdline flag and verify global
mute is triggered.
Verify sequences of switch toggle and suspend/resume.
Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device.
BUG=b:186070097
BRANCH=puff
TEST=Build and make sure TS works to wakeup suspend/resume.
Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The previous "PCIe port" numbering was incorrect and resulted in several
PCIe devices failing to enumerate. With lane reversal, these numbers are
all backwards. This explains the confusing mapping of Clock Source #1 to
Root Port #9 in https://review.coreboot.org/c/coreboot/+/50101. We were
confusing "Root Port" vs "PCIe Lane".
This change addresses the port vs. lane confusion in the device tree
configurations. It also adds more detailed documentation to a future
reader (i.e., me) to avoid this blunder.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I47edf0b0af1bdcf86b89f17ad2a1f128ef9e9f7a
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
After revisiting the genesis GPIO table and schematics for EVT closure,
I discovered several missing and/or incorrectly documented GPIO pin
mappings.
Now the GPIO pin names and functions should match what's written in the
latest schematics.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I73e6733bce761b00717091834c7a49e85154f80b
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51677
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
update the DPTF parameters received from the thermal team.
BUG=b:181627614
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Update fan and thermal settings for ambassador, per recommendations from
Quanta.
BUG=b:177765580
TEST=Built AP firmware
Change-Id: I080859f872caf696f0c085defb8372de658da58a
Signed-off-by: Neill Corlett <corlett@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joe Tessler <jrt@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit f41645c34d8b22a3d887abd56138ae794fc2dfa5.
In Dragonair, during the MP stage, one of the resistors needed
for this functionality has been removed. This results in the
privacy-switch not readable back by the system.
BUG=b:178458332
Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add support LP_16G_2133 SPD for nightfury.
BUG=None
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot
Change-Id: I3709431d8ecb600e25909f456eb0c95db3a3cde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
I2C0 has amplifier connection, thus set it to PchSerialIoPci.
BUG=b:170273526
BRANCH=puff
TEST=Build and check PCH serial IO config is set I2C0 to Mode 1
Change-Id: I9540f7b5538d37de53bcf43531488d714874a565
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH.
PUFF-based variants do not have an internal panel, so do not need this.
Test: build/boot Windows 10 20H2 on google/akemi, verify
display backlight controls functional.
Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updates PCIe registers and GPIO CLKREQ lines to match the schematic.
BUG=b:173566597,b:173567124,b:173566890
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: Ibf519b812022839f749e503436f097d3b48c4383
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Based on USB DB report.
BRANCH=puff
BUG=b:163561808
TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Fan table: provided by the ODM (see attachment in bug) based on
measurements with EVT unit.
BUG=b:173134210
TEST=flash to DUT
Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
"printk()" needs <console/console.h>.
Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:172807539
Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47362
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.
Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.
Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.
Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I320198d56131cf54e0f73227479f69968719b2a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Adds ACPI properties for WDT8762A device.
Per spec v0.8
HID name WDHT2002
T14=100ms
BUG=b:163561649
BRANCH=puff
TEST=emerge-puff coreboot and check system dmesg and evtest can get device.
Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Create the genesis variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172620124
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_GENESIS
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:169840271
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
InternalGfx isn't used so drop it.
Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This setting copy from puff reference board
and should measure again after whole system build.
BUG=b:155261464
BRANCH=puff
TEST=emerge-puff coreboot and check system speaker has sound output.
Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Create the ambassador variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171561514
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_AMBASSADOR
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add internal pull-down for GPP_D19 to improve DMIC noise issue on
nightfury.
BUG=b:171669255
BRANCH=firmware-hatch-12672.B
TEST=Built and checked GPP_D19 voltage after booting
Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Enable ALS ACPI devices for dooly.
BUG=b:168426118
BRANCH=puff
TEST=Ensure that ALS devices are enabled in ACPI tables.
Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
1. Add speaker amplifier ALC1015
2. Enable dmic+ssp registers for speaker and camera DMIC
3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove unused device in Dooly
no SD card reader
no built-in LAN
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Dooly has USBA*2 and USBC*2
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Override unused device
SD card reader, built-in LAN
ALC1015 speaker amplifier SPK_AMP_ON
Update touchscreen/lvds gpio pin
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
A SATA drive may be connected to SATA0.
BUG=b:162909831
BRANCH=puff
TEST=none
Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
1. TSRO trip point from 75C change to 73C
2. Sample period time from 5s change to 60s
BUG=b:160385395
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Sushi is not a real product, just a test of the new_variant program.
The effort to keep it up-to-date with the rest of Hatch is no longer
worth it. Remove the variant.
BUG=b:168030592
TEST=build bot is successful, hatch-cq builds successfully
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Create the dooly variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.2).
BUG=b:155261464
BRANCH=puff
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_DOOLY
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
1. Update paramerters form thermal team.
2. Update PL2 Max/Min to 51W/15W.
BUG=b:167494420
BRANCH=puff
TEST=build noibat and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters receive from the thermal team.
3. Change PL2 min value from 25W to 15W.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
1. Apply the DPTF parameters receive from the thermal team.
2. Change PL2 min value from 25W to 15W.
3. Change PL2 max value from 64W to 51W.
BUG=b:166696500
BRANCH=puff
TEST=build and verify by thermal team
Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
BUG=b:158986928
BRANCH=puff
TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Set tcc offset to 5 degree celsius for kaisa and duffy
BUG=b:166696500
BRANCH=puff
TEST=Build, and verify test result by thermal team.
Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set psyspl2 to 97% of adapter rating, based on our experiment results.
BUG=b:160676773
TEST=Built and check firmware log.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
|
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.
All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.
Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Newer boards have removed the second temperature sensor
and relocated the remaining sensor.
BUG=b:162909373
TEST=Confirm on hardware.
Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Some smart battery patches have been backported to the ChromeOS 4.19 kernel,
and userspace can now access smart battery data from sysfs instead of using
the hacky ectool instead.
Also change all space indents into tab indents while we're here.
BUG=chromium:1047277
TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2.
BRANCH=none
BUG=b:150515720
TEST=build and check the USB3 gen2 register on DUT is correct.
Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Fix a missing CONFIG_ prefix in Makefile.
BUG=b:161154280
BRANCH=puff
TEST=builds
Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11
Spotted-by: Ryan Lin.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Screen flickered on VT2 on some devices after idle a period of time.
Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.
Because CB:38212 (commit eae254e) caused this issue.
BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered
Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
V.2: Spare USB routed internally to another peripheral and so
no plug event hook needed.
BUG=b:1603699358,b:157479891
BRANCH=none
TEST=none
Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:160296662
BRANCH=none
TEST=none
Change-Id: I5298e1779461995a98722099b397692351767089
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:160295948
BRANCH=none
TEST=none
Change-Id: I3600340d3448457942c827a463b458b280fea19a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
BUG=b:160296661
BRANCH=none
TEST=none
Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:160296325
BRANCH=none
TEST=none
Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify DPTF parameters for faffy from thermal team.
BUG=b:160292247
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
verify the parameters are correct
Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Override VBT for nightfury SKU_ID = 2 to support different panel.
BUG=b:159051021
BRANCH=firmware-hatch-12672.B
TEST=Built and verified using different VBT by SKU_ID
Change-Id: I9450814aadc43cc7991457c3793f109b889186b9
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I13626a236f1b7385208c4181150f094cbda490ed
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.
BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This reverts commit 1408798637125f1707ded7215e22461c623a79a8.
Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause.
BUG=b:159370566
BRANCH=None
TEST=boot up device and make sure when kernel is booted, backlight comes up.
Change-Id: I643854c6c805d262539bbb482808e8c322059a49
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.
Delay with Power Cycle or Global Reset:
Existing behaviour:
S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch:
S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.
Test=Verified on Hatch and Puff boards
BUG=b:158634281
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
V.2: Manually modified to keep Kconfig sorted.
BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.
BUG=b:149714955
TEST=lid/base touch screen works correctly
Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.
Customizations can be done later via introducing a devicetree
parameterisation.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|