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path: root/src/mainboard/google/hatch/variants/hatch_whl
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2019-07-21mb/google/hatch: Remove hatch_whlPhilip Chen
Hatch_whl variant is deprecated. BUG=b:137180390 Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen andFrank Wu
increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-20mb/google/hatch: Remove unused USB2 port5 from baseboard devicetreeAamir Bohra
Hatch newer board revision do not use USB port5 for discrete BT. Hence remove the port configuration and UBS2 P5 asl entry. The older board version would continue to use USB2 P5 hence moved the entry to overridetree.cb Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-06-16mb/google/hatch: Move memory strap GPIOs under variant gpio headerAamir Bohra
Move the memory strap gpios to variant/gpio.h, as the memory straps are different for helios. Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-14hatch: Fix pen eject wake polarityTim Wawrzynczak
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing devices to wake up on pen insertion instead of removal. Changed to EV_ACT_DEASSERTED. BUG=b:134547896 BRANCH=none TEST=Verified in OS, device only wakes up on pen removal Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10mb/google/hatch: Fine tune Goodix touch screen timingDtrain Hsu
According to Goodix GT7375P datasheet, reduce Goodix touch screen timing. BUG=b:129727745 BRANCH=None TEST=local build and tested with Goodix touch screen worked under coldboot (10 times), warmboot (10 times), S3 (10 times). Change-Id: I4bf081bab5e89d3ce336c6432da5ba71279fa98d Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-05-06mainboard/google/hatch: Enable PEN_EJECT_L as wake & notify source.Tim Wawrzynczak
Updated GPP_A8 to be a GPI and SCI source, to support both wake and notifications. BUG=b:128941098 BRANCH=none TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest and waking from s0ix confirm this works. The output of /proc/interrupts confirms the correct interrupt is triggered. Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-30mb/google/hatch: Modify IRQ configuration to enable RT5682 headset INTNaveen Manohar
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT. Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support jack triggering on both edges. BUG=b:130180492 TEST=build and boot on a CML EVT board. Use evtest & verify headset jack detection functions as expected. Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Suggested-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-25mb/google/hatch: Pull up GPP_C13 for hatch and hatch_whlPhilip Chen
On EC end, we want to change this pin from push-pull to open-drain. And since there is no external pull-up resistor on the board, we'll have to configure this pin as internal-pull-up on AP end. BUG=b:129306003 TEST=None Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24mb/google/hatch: Move SD card detect GPIO.Tim Wawrzynczak
Not all Hatch variants utilize the SoC's native SD card support. Move the support to board-specific variants instead of the base device tree. BUG=none BRANCH=none TEST=compiles (no Hatch device to test with) Change-Id: Iae24114aad2c4d042c25da6f8cb740ccc8960082 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32417 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13mb/google/hatch: Restore Goodix Touch ScreenEric Lai
Restore Goodix devicetree config because of the missing Goodix config when moving from baseboard devicetree to board level overridetree. And move PENH from I2C#2 to I2C#1. BUG=b:124460799 BRANCH=None TEST=local build and tested with Goodix touch screen Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-12mb/google/hatch: Use GPIO IRQ for sx9310 deviceFurquan Shaikh
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is the interrupt line for sx9310. This is required because IRQ# used by GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing. Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6 is currently unused in the devicetree. BUG=b:129794308 TEST=Verified that there are no interrupt storms on GPP_A0. Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-04mb/google/hatch: Move I2C/SPI options to override treeFurquan Shaikh
This change moves the I2C/SPI devices and configs which do not apply to all variants to override tree. Currently, there are just two variants. However, as we prepare to add more variants, these devices need to be moved out of the base devicetree. BUG=b:129728235 TEST=Verified that I2C/SPI devices are present in static.c for hatch and hatch_whl. Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Update DRAM IDsShelley Chen
Update Hatch DRAM IDs to use the new DRAM ID assignment for general spds: 0 = 4G 2400 1 = 4G 2666 2 = 8G 2400 3 = 8G 2666 4 = 16G 2400 5 = 16G 2666 BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08mb/google/hatch: Create hatch_whl variantShelley Chen
In preparation for the transition of hatch from WHL to CML, we are creating a checkpoint called hatch_whl that we can use for creating firmware compatible with the WHL hatch variant. BUG=b:127310803 BRANCH=NONE TEST=NONE Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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