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Updates PCIe registers and GPIO CLKREQ lines to match the schematic.
BUG=b:173566597,b:173567124,b:173566890
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: Ibf519b812022839f749e503436f097d3b48c4383
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.
Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.
Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.
Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the genesis variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172620124
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_GENESIS
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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