coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-08-23	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	Nico Huber
2020-08-07	soc/intel/cnl: Set Heci1Disable depending on devicetree config	Felix Singer
2020-07-20	mb/google/puff: update USB3 gen2 parameters	Tim Chen
2020-07-03	mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Duffy	Edward O'Callaghan
2020-06-23	mb/google/hatch: Make puff and variants share common mainboard.c	Edward O'Callaghan
2020-06-22	mb/google/hatch: Make puff and variants share common dptf.asl	Edward O'Callaghan
2020-06-22	mb/google/hatch: Make puff and variants share common ec.h	Edward O'Callaghan
2020-06-17	mb/google/puff: add MST and LSPCON details to variants devicetree	Shiyu Sun
2020-06-14	mb/google/hatch/vr/puff: Set up PL2 and PsysPL2	Tim Chen
2020-06-12	mb/google/puff: Update i2c[2] and i2c[3] rise and fall times	Sam McNally
2020-05-26	cannonlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-26	intel/cannonlake: Implement PCIe RP devicetree update	Nico Huber
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-05-01	mb/google/hatch/vr/puff: Add psys_pmax calculation	Tim Chen
2020-04-30	mb/google/puff: update USB2 strength	Tim Chen
2020-04-24	mb/google/hatch: Add Duffy variant specific DPTF parameters	Edward O'Callaghan
2020-04-23	mb/google/puff: Switch USB2 port1 and port3	Tim Chen
2020-04-21	mb/google/puff: configure USB PLD groups	Peter Marheine
2020-04-20	security/vboot, mb/google: Fix build errors	Patrick Georgi
2020-04-15	mb/google/hatch: Add Duffy variant	Edward O'Callaghan