summaryrefslogtreecommitdiff
path: root/src/mainboard/google/guybrush
AgeCommit message (Collapse)Author
2021-07-15mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a defaultMartin Roth
To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12mb/google/guybrush: enable psp_verstage by defaultKangheui Won
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-29mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth
To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth
This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth
This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-28mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth
When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/guybrush: Change ACPI HID for machine driverYu-Hsuan Hsu
To avoid from using same the name AMDI5682 as Zork, changing to use AMDI1019. The corresponding kernel change is on CL:2929864 BUG=b:189297564 TEST=Audio works with the corresponding kernel change. Cq-Depend: chromium:2929864 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/guybrush: configure eSPI mux on psp_verstageKangheui Won
Temporarily set eSPI mux in verstage_mainboard_early_init. Ideally cezanne code should have common function to do this and mb-specific code would just call it, but for now PCI access doesn't work in the PSP so we can't do it. AMD team confirmed that the current PSP doesn't configure LPC so we don't have to disable LPC when configuring eSPI mux so we can temporarliy skip the LPC part here. BUG=b:183149183 TEST=boot guybrush with psp_verstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-23mb/google/guybrush: Indicate the presence of ACP DMICKarthikeyan Ramasubramanian
In order to enable ACP DMIC hardware runtime detection, indicate that ACP DMIC is present. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated in the ACP device. Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/google/guybrush: Add guybrush specific AMDFW config fileMartin Roth
This takes the "generic" AMD firmware config file from the cezanne directory and removes pieces unnecessary for guybrush. Removed: - PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin - PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin - PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin - DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin - PSP_MP2CFG_FILE MP2FWConfig.sbin BUG=b:187103438 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-22mb/google/guybrush: Only enable early port80s if using psp_verstageMartin Roth
PSP_Verstage will enable eSPI early in the boot sequence. If the platform isn't using psp_verstage, the system can hang on the first port 80h postcode that comes out because they aren't routed to an active device until eSPI is configured. BUG=b:191370340 TEST=Build without PSP_Verstage, verify system doesn't hang. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/guybrush: Add devfn macros for devices on GPP bridgeKarthikeyan Ramasubramanian
Add devfn macros for some peripheral devices that are attached to PCIE GPP Bridge. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I7c5433dff2329f13c282908e2b848405819347ff Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-21mb/guybrush: Probe FW_CONFIG for FP_PRESENTRob Barnes
Only enable fingerprint device when FP=FP_PRESENT in FW_CONFIG. BUG=b:186685292 TEST=Boot guybrush, no "EC failed to respond in time" error Change-Id: Ifaea9e23e6cdfdae024464ff36c1520b8ad05e50 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-17mb/google/guybrush: Add helpers for cbi fw_config settingsMartin Roth
Turn on CBI and add helper functions for determining the board configuration from the firmware config settings in CBI. BUG=b:187316460 TEST=Built Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/*: Fix some indirect includesKyösti Mälkki
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14mb/google/guybrush: Update memory configurationIvy Jian
Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks. BUG=b:190692797 TEST=Build and boot to OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-11mb/google/guybrush: Add EC_HOST_EVENT_HANG_DETECT to wake maskRob Barnes
Add EC_HOST_EVENT_HANG_DETECT to S3/S5/S0ix wake mask. This event is sent when the EC detects the AP didn't fully enter a sleep state. BUG=b:186571086 TEST=Trigger hang detect while AP is in S0ix, AP wakes from S0ix Change-Id: I09ccf609fc453c19b4fb1ddaa5a0c86d7a85aad1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-10mb/google/guybrush: Move variant_has_fpmcu() after eSPI initMartin Roth
Currently variant_has_fpmcu() is called very early in bootblock, before eSPI is initialized. When checking CBI for its presence, that causes an error and nothing else can be read from CBI in bootblock. Moving it slightly later in bootblock doesn't hurt anything from a timing standpoint, and allows CBI to be read. BUG=None TEST=See CBI get read and the FPMCU field read correctly. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-08mb/google/guybrush: Enable RTD3 support for NVMeRaul E Rangel
This will tell the kernel to ignore PCI ASPM when suspending the device and instead place the device into D3. We don't actually have a pin to control power to the NVMe so we leave it in D3Hot. I'm not sure if `PCI_RST#` is working correctly on S0i3 suspend/resume. If it's not acting as expected we can add the reset GPIO and have the OS do it. BUG=b:184617186 TEST=Run suspend_stress_test on guybrush for 10 cycles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29539ac120a9f1b7c1bfeaca745cfc82acfa461a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54967 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07soc/amd/cezanne: Configure I2C Pad RX Select through devicetreeKarthikeyan Ramasubramanian
Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree. BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard. Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-07mb/google/guybrush/var/guybrush: Update GPIO configurationKarthikeyan Ramasubramanian
Some of the GPIOs are either re-purposed for different use-cases or are unused in upcoming board phase (board version 2). Update the GPIO configuration accordingly. Here are the GPIOs that are updated: GPIO Board Id 1 Board Id 2 ============================================= GPIO31 TP183 EN_SPKR GPIO69 EN_SPKR SD_AUX_REST_L GPIO70 SD_AUX_RESET_L Unused TP27 GPIO74 RAM_ID_CHAN_SEL Unused TP49 BUG=b:189327557, b:188542649, b:188542497 TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is detected fine in Board ID 1. Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-07psp_verstage: initialize i2c in soc_initKangheui Won
GSC is connected with AP via i2c bus so we need to enable i2c in psp_verstage. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifierKarthikeyan Ramasubramanian
In order to resolve the I2C address conflict with another peripheral in the upcoming hardware build, left speaker amplifier I2C address is reconfigured. BUG=b:188539052 TEST=Build Guybrush mainboard. On Guybrush board ID 1, all the 3 speaker amplifiers are added to the ACPI table. \_SB.I2C2.D028: Realtek SPK AMP L at I2C: 03:28 \_SB.I2C2.D029: Realtek SPK AMP R at I2C: 03:29 \_SB.I2C2.D02A: Realtek SPK AMP L1 at I2C: 03:2a At the OS side, the concerned speaker amplifiers are probed and enumerated. localhost ~ # i2cdetect -y -r 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- -- 20: -- -- -- -- -- -- -- -- UU UU -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27mb/google/guybrush,mancomb: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5cbc620001d3c21c538b62ab2811b6e07269feb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54962 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/google/guybrush: set PSPP policy to powersaveFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26src/mainboard/google/guybrush: update devicetree with USB settingsJulian Schroeder
All relevant USB phy settings can now be controlled via devicetree. The given values are the AMD default ones. For proper tuning procedure and values contact AMD. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: Ie8d08bde54f8c0cb8202ba111b9c7a9bd33fa03e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-25mb/google/guybrush: Add Goodix touchscreenIvy Jian
Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:188872893 TEST=build and boot into OS. check dmesg trying to add GDIX0000:00 device. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I38c9bbf6e1c1531bf3524552db58c0bf183acbb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-21mb/google/guybrush: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/guybrush: Add SoC thermal zoneRaul E Rangel
The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-14mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSIONIvy Jian
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:187904819 TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-12mb/google/guybrush: Configure wake resource for WiFiKarthikeyan Ramasubramanian
In order to support wake on WLAN events, configure the wake resource. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource is added to SSDT. Device (\_SB.PCI0.GP20.WF00) { Name (_UID, 0x38B82CBC) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.GP20.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x08, 0x03 }) } Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-12mb/google/guybrush,mancomb: Adjust GBB size to 12KBMartin Roth
The 448KB size of the GBB is larger than is needed, so adjust it down to the minimum size needed. BUG=b:186761897 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7a24945cd9ecc8872871f57b09ca71fc40e92473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-10mb/google/guybrush: Enable GFX HDA deviceKarthikeyan Ramasubramanian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-10mb/google/guybrush: Enable PP5000_PENEric Peers
Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers@google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-09mb/google/guybrush: Populate PIC IRQ dataRaul E Rangel
The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/google/guybrush: Switch eSPI ALERT# to in-bandRaul E Rangel
Using the push-pull alert was causing leakages when in S0i3. This is because the EC drives ALERT#, so when the AP enters S0i3, the extra current leaks into the SoC and ends up turning on the power regulators. By using in-band ALERT#, the EC no longer drives this pin high, thus fixing the leak. We could also have used an open drain alert, but the rise time is less than ideal. BUG=b:187122344, b:186135022 TEST=Measure S0i3 power on guybrush and validate it's no longer high. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05mb/google/guybrush: Configure Pen Detect deviceKarthikeyan Ramasubramanian
Pen Detect GPIO is exported through GPIO keys driver to the kernel so that stylus tools is popped on pen eject event. Hence enable the GPIO keys driver and configure the devicetree. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is added to the ACPI SSDT table. Ensure that the Pen Eject events are detected. Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1620159356.243180, -------------- SYN_REPORT ------------ Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Ensure that when the device is suspended, it wake on Pen Eject event and does not wake on Pen Insert event. Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05mb/google/guybrush: Fix S0i3/S3 GPIO configurationRaul E Rangel
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=Wake system from S0i3 with EC and see GPE 3 increment. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-30mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE codeMartin Roth
Guybrush is pretty definitely alive, so this can be removed, as the TODO line said. BUG=180721202 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/guybrush: update the telemetry settingChris Wang
Update the telemetry setting for guybrush vddcrvddfull_scale_current : 92165 #mA ddcrvddoffset : 412 vddcrsocfull_scale_current : 30233 #mA vddcrsocoffset : 457 BUG=b:182754399 TEST=Build, boot to guybrush Change-Id: Ib92bb169693634665fc8e165837e7ae3e6137bcf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52736 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpiFelix Held
guybrush and mancomb don't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/guybrush: Configure Audio Co-processorKarthikeyan Ramasubramanian
Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix the scope in which ACP is defined in the devicetree. BUG=b:182960979 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29mb/google/guybrush: Set system_config to 2 for guybrush boardsMartin Roth
All guybrush boards should have system_configuration set to 2, so put this in the main devicetree. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com>
2021-04-27mb/google/guybrush: Fix EC SCI configurationRaul E Rangel
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. BUG=b:186045622, b:181139095 TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I764b9ec202376d5124331a320767cbf79371dc07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-26mb/google/guybrush: Add STAPM values to overridetreeMartin Roth
This enables STAPM power management. Values follow the AMD specification. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23mb/google/guybrush: Update memory configurationMartin Roth
The next guybrush build uses 2 new LPDDR4X memory chips: - Micro MT53E1G32D2NP-046 WT:B - Hynix H9HCNNNBKMMLXR-NEE The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X list since the last time guybrush was updated, so that's brought into the guybrush SPD directory as lp4x-spd-10.hex, but it's not used. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-22guybrush: Increase eSPI bus frequency to 33MhzRob Barnes
Change eSPI bus frequency to 33Mhz. BUG=b:184356693, b:185514521 TEST=Boot guybrush, observe no eSPI bus errors Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/guybrush: Implement tis_plat_irq_statusRaul E Rangel
BUG=b:185397933 TEST=boot guybrush and no longer see tis_plat_irq_status warnings Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/guybrush: Sort VBOOT_EARLY_EC_SYNCRaul E Rangel
BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/guybrush,mancomb: include soc/gpio.h in baseboard/gpio.hFelix Held
This include provides the GPIO_x definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12a0d95f79658f3852132876e92c389b715f3001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/guybrush,mancomb: use EC_SCI_GPI in espi_sci_sources structFelix Held
The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that definition in all places in the mainboard code instead of a mix of the board specific define and the SoC's GEVENT number define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Unmask eSPI keyboard IRQRaul E Rangel
PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Remove PS/2 mouse configRaul E Rangel
Guybrush doesn't have a PS/2 mouse. BUG=none TEST=boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: PCIe GPIOs - enable enables, disable resetsMartin Roth
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush/port_descriptors: add dummy descriptorsFelix Held
This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptorsMartin Roth
pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/guybrush: add DXIO and DDI descriptorsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-06Revert "mb/google/guybrush: Disable GFX"Raul Rangel
This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-06mb/google/guybrush: Disable GFXRaul E Rangel
This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/guybrush/var/guybrush: Add Codec and Speaker configrationKarthikeyan Ramasubramanian
Enable I2C2 in devicetree and fill ACPI information for Codec and Speaker amplifiers. Pass correct IRQ GPIO for headset jack. BUG=None BRANCH=None TEST=Ensure that the Codec and Speaker Amplifiers are detected in i2cdetect. Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/guybrush: Add Bluetooth configurationKarthikeyan Ramasubramanian
Configure the BT disable GPIO to logic low in order to enable Bluetooth. Add USB ACPI configuration for BT device. BUG=b:182201890 TEST=Build and boot to OS. Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05mb/google/guybrush: Enable camera power GPIOIvy Jian
Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05mb/google/guybrush: Update GPIO configurationMartin Roth
Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mb/google/guybrush: Enable early EC Software SyncKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync is complete. Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-02mb/google/guybrush: Add Elan Touchpad configurationKarthikeyan Ramasubramanian
Enable Touchpad by configuring the enable GPIO to logic high. Add touchpad configuration for ELAN touchpad. BUG=b:182207444 TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events are detected using evtest. Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01mb/google/guybrush: Add IRQ numbersRaul E Rangel
BUG=b:183737011 TEST=cat /proc/interrupts and see i2c controllers and gpio controller listed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b2f23b2c2a7c4cec198276814d80f545e85aa41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-31mb/google/guybrush: Enable VBOOT_LID_SWITCHRaul E Rangel
Needed so get_lid_switch will actually call the EC. Otherwise it returns -1. BUG=b:183524609 TEST=Depthcharge no longer halts complaining that coreboot didn't sample the pin Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-31mb/google/guybrush: Switch eSPI to 16 MHzRaul E Rangel
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16 MHz makes everything a lot more stable. BUG=b:183524609 TEST=Boot to OS and run `ectool version` 1000 times and see no problems. Before with 33 MHz there was an error every few cycles. declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i" Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-03-29mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PINFelix Held
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select it and remove the temporary workaround that was implemented in the mainboard code in commit 39ef89033624a2d14b0c77cdbdf287dd7d7059e1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29mb/google/guybrush: Enable DISABLE_SPI_FLASH_ROM_SHARINGRaul E Rangel
Guybrush uses GPIO67 as an input. BUG=none TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10068bb6870b2cb96033cf3893cde71db5c1d709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51781 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: Temporary fix to set eSPI muxMathew King
This change allows guybrush EC communication while other patches in the SOC code are worked on. BUG=b:183149183 TEST=Boot guybrush with EC comunication Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable PCIe devices in devicetreeMathew King
BUG=b:181690884 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Add guybrush APCBs into buildMartin Roth
This adds the Guybrush APCBs into the AMD firmware binary. BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13mb/google/guybrush: Add ACPI support for Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Configure eSPI GPIOs in early stageMathew King
BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure early GPIOs in earliest stageMathew King
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 22:03:47 +0000