diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-06 22:17:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-07 22:50:24 +0000 |
| commit | c81fb7ca94e84bf1086756d0e5b4fad9adb75658 (patch) | |
| tree | d8eff91ad0e1da2617867dba9f4ed68112598e93 /src/mainboard/google/guybrush | |
| parent | d76b4f6607ba233358b7eb481d098b3abbaafedb (diff) | |
mb/google/guybrush/port_descriptors: add dummy descriptors
This is a temporary workaround for a bug that breaks graphics due to
some power management issue.
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/guybrush')
| -rw-r--r-- | src/mainboard/google/guybrush/port_descriptors.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 322781238d..cc1fa1a7b2 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -53,6 +53,28 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .clk_req = CLK_REQ3, .gpio_group_id = GPIO_40, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 5, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} } }; |