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2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-05mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD dataChris.Wang
The value at offset 329 should be: 0x4B -> "K" not 0x48 -> "H" in ASCII code. BUG=b:224884904 TEST=Build, confirm the part number is matched the corresponding parts Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05mb/google/guybrush/var/dewatt: Override SPD file for Samsung partsRobert Zieba
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This commit overrides the default SPD files used for these parts BUG=b:224884904 TEST=Verified that Dewatt SKU1 and SKU3 boot with changes Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-01mb/google/guybrush: Remove elog_gsmi_cb_mainboard_log_wake_sourceRob Barnes
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. BUG=b:227163985 BRANCH=gubyrush TEST=No 164 errors detected during suspend_stress_test /sys/firmware/log output after resume before change: SMI# #1 ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC Chrome EC: clear events_b mask to 0x0000000000000000 after change: SMI# #6 ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/google/guybrush/var/dewatt: add specific SPD hex for dewattChris.Wang
Add the specific SPD hex file for the Samsung memory part with updating the part number into the SPD table. The ABL needs to identify the part by checking SPD data to do the proper tuning. BUG=b:224884904 TEST=Build, validate the SPD data has been applied. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-30mb/google/guybrush: Disable EN_SPKR on initYu-Hsuan Hsu
We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot guybrush and verify the devbeep and gpio value in kernel Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30mb/google/guybrush/var/dewatt: Update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt EVT: vdd scale: 91288 vdd offset: 279 soc scale: 29785 soc offset: 461 BUG=b:219626910 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Change-Id: I4456ffddbf9963f1202a349abe52df2bbb726468 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63136 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung partsRobert Zieba
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This commit assigns them exclusive IDs 9 and 11 to facilitate this. BUG=b:224884904 Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 73331 -> 94623 VDD offset: 1893 -> 1847 SOC scale: 31955 -> 29904 SOC offset: 852 -> 756 BUG=b:217963719 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18mb/google/guybrush/port_descriptors: use enum values for link speedFelix Held
Use GEN3 from enum dxio_link_speed_cap instead of the number 3. TEST=Timeless build results in identical firmware image for guybrush Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-15mb/google/guybrush/var/nipperkin: update APU STT settingKevin Chiu
BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCKRaul E Rangel
The verstage.c file contains PSP verstage specific code. We don't need it when using x86 verstage. BUG=b:193050286 TEST=Build and boot guybrush with x86 verstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/guybrush: Enable DEBUG_SMI for non-serial firmwareRaul E Rangel
In order to copy the PSP verstage logs into x86 cbmem, we need to enable DEBUG_SMI. This will include the CBMEM console code in SMM. I only enable DEBUG_SMI when UART is disabled because SMM doesn't currently save/restore the UART registers. This will result in clearing the interrupt enable bits and makes it so you can no longer use the TTY. BUG=b:221231786, b:217968734 BRANCH=guybrush TEST=Build serial and non serial firmware and verify DEBUG_SMI is set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10mb/google/guybrush/var/nipperkin: turn off WWAN DPRKevin Chiu
Sets GPIO 42 to high to turn off WWAN DPR BUG=b:216735313 BRANCH=guybrush TEST=emerge-guybrush coreboot make sure GPIO42 is high Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRMKarthikeyan Ramasubramanian
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2. But it is programmed incorrectly in the concerned ACPI device. Pass the correct GPIO. BUG=b:204401306 TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object contains the right GPIO. Ensure that the screen visibility gets updated by pressing the privacy screen button. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-01mb/google/guybrush/var/nipperkin: update thermal settingKevin Chiu
Enable STT and decrease sustained_power_limit_mW to 12W BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-25mb/google/guybrush: enable coreboot to request spl fuseJason Glenesk
Enable guybrush based platforms to send fuse spl command to PSP when required. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Confirm that PSP indicates fusing is required, and confirm coreboot sends command. Fusing is required when the image is built with an SPL table requiring newer minimum versions. A message indicating fusing was requested will appear in the serial log. "PSP: Fuse SPL requested" Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros
Guybrush platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. With this change in place it is important to use correct kernel version which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3 available and thus TPM device available in OS, what may end up as a serious error - guybrush refuses to boot without access to TPM. BUG=b:204508404 BRANCH=guybrush TEST=Build proper kernel and firmware. Run on guybrush and verify TPM functionality. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15mb/google/guybrush: Add a mainboard specific SPL tableZheng Bao
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-14mb/google/guybrush: Enable power resource for BTRaul E Rangel
The `reset` gpio is currently being consumed by the btusb kernel driver. The functionality was added in https://crrev.com/c/3342774. The goal of the patch was to reset the BT device when command timeouts occur. This works, but it doesn't support the case where the BT device is having problems with USB enumeration. In that case the device can't enumerate so the driver can't help resetting the device. If we instead switch to using an ACPI power resource, the kernel can control the BT device's power. This is beneficial when the device is having USB communication problems since the kernel will try and power cycle the device. We don't lose the ability to reset the device on command timeouts either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if there is no `reset` GPIO. So win / win. This results in the following power resource: PowerResource (PR02, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x84) Sleep (0x01F4) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.STXS (0x84) Sleep (0x0A) } } I switched the device tree entry from using reset_gpio to enable_gpio because the acpi_device_add_power_res method asserts the reset in the _ON method unconditionally. This results in a small glitch on the line. By using the enable_gpio we get the correct behavior. I don't have a datasheet right now, so I just picked some values for the reset timing. The kernel driver was using 200ms. We can revisit the numbers when we get a datasheet. BUG=b:218295688 TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power resource is created on the kernel. This should allow the kernel to power cycle the device via usb_acpi_set_power_state. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-12mb/google/guybrush/var/nipperkin: Add _HID for privacy screen deviceKevin Chiu
BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot dump SSDT, see _HID instead of _ADR Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-08mb/google/guybrush: Fix trackpad SCI configKarthikeyan Ramasubramanian
Trackpad GPIO configuration does not align with the IRQ configuration in the devicetree. Configure the trackpad GPIO to generate SCI on falling edge. BUG=None TEST=Build and boot to OS in Nipperkin. Ensure the trackpad is functional. Suspend the device and wake it using trackpad. Perform suspend/resume sequence for 100 iterations. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If4324e09535d2676c8a8c6643604227eeaba0fe8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-08mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel
This will make debugging boot failures with a non-serial firmware easier. If we encounter an error that requires a reboot, this will dump the entire CBMEM contents onto the UART. This is especially helpful during S0i3 resume because the PSP verstage console logs are not exposed anywhere. BUG=b:215599230 TEST=Cause verstage error in S0i3 with non-serial firmware and see that the verstage logs were dumped to the UART before rebooting. Entering PSP verstage S0i3 resume tpm_setup failed rv:1 VB2:vb2api_fail() Need recovery, reason: 0x3f / 0xcc Saving nvdata Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-07mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 supportChris Wang
Add ID "AMDI5619" for machine driver to support ALC5682I-VS + ACL1019 combination. BUG=b:211835769 TEST=Build dewatt, codec is functional with new machine driver. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used tableRob Barnes
With the APCB edit tool enabled in commit 6a3ecc5 (guybrush: Inject SPDs into APCB), DeWatt and Nipperkin can have independent mem_parts_used tables. Copied common table from guybrush and ran part_id_gen to make sure it's synced to latest. BUG=b:209486191 BRANCH=guybrush TEST=Boot on nipperkin Change-Id: Id30b596c2466902dfcc59dcc88dcaa00748a3949 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-02mb/google/guybrush: Enable PSP port 80sRaul E Rangel
Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-31mb/google/guybrush/guybrush: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c BUG=b:215432928 Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-26mb/google/guybrush/var/dewatt: Update Elan touchpad interrupt triggerKenneth Chan
Update Elan touchpad interrupt trigger to level low from edge low to keep consistency with Synaptics touchpad. Checked with Elan PM Iris and other projects(spherion), the touchpad can be set to edge or level low trigger. Sepherion Elan touchpad IRQ setting: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.4/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi;l=415?q=mt8192-asurada.dtsi&ss=chromiumos%2Fchromiumos%2Fcodesearch:src%2Fthird_party%2Fkernel%2F BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Elan and Synaptics touchpad wakeup from s0i3 well with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ifac49b131cadc1f8838bb6243ad6d17feb272bd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26mb/google/guybrush/var/dewatt: Update touchpad GPIO configurationKenneth Chan
Update GPIO configuration to fix Synaptics touchpad can't wakeup system from s0i3. BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Synaptics touchpad wakeup from S3 with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I29734595d37283adc6fd4a0ed17f51a5c9061796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26mb/google/guybrush/dewatt: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. get_cpu_count() == 4 && get_threads_per_core() == 2: This case is for 2 Core and 4 Thread CPU (2C/4T for short). get_cpu_count() == 2: This is for 2C/2T. This is for a possible future case. BUG=b:208677293 Change-Id: I8d0fa96818a768b7960d92821b927dbc622675ae Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-25mb/google/guybrush/var/nipperkin: Add Board values for eDP tuningZheng Bao
Reference test document, update tuning registers from pass experiment setting of phy_settings. The document about eDP tuning can be gotten from the issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-24mb/google/guybrush: Change DDI settings for guybrush variantsZheng Bao
Like the variant function to change DXIO settings, add a similar weak function to modify the DDI settings. Currently we follow the old way. Later we will find out a better way to avoid using weak function. Change-Id: I9898d717bc3025ea1ddc3b0db41325083324ed57 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-22mb/google/guybrush/var/nipperkin: turn on WLAN ASPM L1ssKevin Chiu
BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot WLAN works properly in OS Change-Id: Ie1f295eaa57af7c2942e1807b3a0c4dcd89cd696 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-14soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-12mb/google/guybrush/var/dewatt: Update unused GPIO pinsKenneth Chan
According to H/W schematics, fingerprint, SD controller, WWAN/LTE and PEN modules are not stuffed and hence the following GPIOs are marked as not connected: GPIO_3 : TP247 GPIO_4 : TP218 GPIO_5 : TP220 GPIO_8 : TP245 GPIO_11: TP244 GPIO_17: TP194 GPIO_18: TP195 GPIO_21: TP243 GPIO_24: TP196 GPIO_31: TP50 GPIO_42: TP219 GPIO_69: TP217 GPIO_115: TP235 GPIO_116: TP205 GPIO_140: TP226 GPIO_142: TP225 GPIO_144: TP227 BUG=b:204155627 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I552fd6af1cd827e4e41be1a954bf95c3afbb6a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-12mb/google/guybrush/var/dewatt: Support ALC5682I-VS codecKenneth Chan
ALC5682I-VS codec will be used in EVT, replacing ALC5682I-VD. BUG=b:211835769 TEST=emerge-guybrush coreboot chromeos-bootimage; HW reworked a proto MB with ALC5682I-VS, build and check "i2cdetect -r -y 2", dmesg. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ib1a82285b60c6d5d474ead8643a826e36f56f5b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-10src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS
Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: I50fcbb16895662c7451fec1569a8a61398792531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10guybrush: Inject SPDs into APCBRob Barnes
Inject SPDs into APCB at coreboot build time. BUG=b:209486191 BRANCH=None TEST=Boot guybrush and nipperkin with injected APCB Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-06mb/google/guybrush/var/dewatt: update USB3 settings for passing SIKenneth Chan
Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-06mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changedKenneth Chan
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3354766. Update to matched id for audio work normal. 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2. BUG=b:210542422 TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I542f886fe63205777837d7146169177b043cc5f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane ParameterKevin Chiu
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment" per port: port#0: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#1: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#4: COMPDISTUNE0: 0x1->0x6 / TXVREFTUNE0: 0x3->0xE port#5: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 BUG=b:203049656 BRANCH=guybrush TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. pass USB eye diagram verification Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04mb/google/guybrush/var/dewatt: disable unused PCIe clock settingKenneth Chan
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush. Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt. BUG=b:211566312 TEST=emerge-guybrush coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: If449453bc60ed41e104346429babc06a73acef64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-26mb/google/guybrush/var/dewatt: update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt: vdd scale: 95359 vdd offset: 449 soc scale: 31481 soc offset: 193 BUG=b:211566312 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/guybrush/var/dewatt: update DRAM ID tableKenneth Chan
1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL 2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants) BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for ↵Kenneth Chan
USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-20mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGERob Barnes
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-18mb/google/guybrush: Disable GPIO export for Goodix TouchscreenRaul E Rangel
We want ACPI to own the GPIOs. This will stop the GPIOs from being exposed to the OS driver. BUG=b:209705576, b:210694108 TEST=Dump ACPI table and verify GPIO are no longer in _CRS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-17mb/google/guybrush/var/nipperkin: config eSPI as dedicated alertKevin Chiu
Setup eSPI to dedicated alert per the latest schematic changes. DUT won't hang up at power on boot due to eSPI alert is triggerred unexpectedly. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage test power on/reboot on DUT (6 units) each 10 loops->pass Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-16mb/google/guybrush/var/dewatt: Add audio codecKenneth Chan
Add ALC5682I-VD and ALC1019 for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie4d21a11377c73b913a8f79a92d5869ea70f4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-15mb/google/guybrush: Set TPM to to be kernel power managed.Rob Barnes
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause the TPM kernel driver to send a shutdown command before s0i3 entry. This change depends on S0i3 verstage running and reinitializing the TPM. BUG=b:200578885 BRANCH=None TEST=TPM shutdown sent during s0i3 entry on guybrush Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM tableKevin Chiu
add Hynix H54G56CYRBX247 support BUG=b:210365851 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage power on successfully Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13mb/google/guybrush/var/dewatt: Add Elan touchscreenKenneth Chan
Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5) BUG=b:208373433 TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13mb/google/guybrush/var/dewatt: Add Synaptics touchpadKenneth Chan
Add Synaptics S9831 touchpad for dewatt. BUG=b:208182457 TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Configure Smart Card in normal modeKarthikeyan Ramasubramanian
As per the schematics, smart card is expected to operate in normal mode by default. So configure the SOC_SC_PWRSV gpio accordingly. BUG=b:202992077 TEST=Build and boot to OS in Nipperkin board version 2. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-08mb/google/guybrush: Combine mem_parts_used.txtRob Barnes
Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstageKarthikeyan Ramasubramanian
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID straps and Developer Mode Beep signals. During boot up it is LOW and selects RAM_ID straps. When the system enters OS, it is driven HIGH and selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5 domain it does not reset until the system enters mechanical off (G3) state. On scenarios where the power button is pressed when the system is in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still selecting DEV BEEP signal. This causes boot up failures. Fix this by configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage. BUG=b:204450368 TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle followed by a S5 -> S0 boot cycle for 2 iterations successfully. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01guybrush: add RO_GSCVD area to FMAPVadim Bendebury
This area is used for storing AP RO verification information. BRANCH=none BUG=b:141191727 TEST=built a guybrush firmware image and verified that the RO_GSCVD area was indeed added: $ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \ grep -B3 RO_GSCVD area: 25 area_offset: 0x00808000 area_size: 0x00002000 (8192) area_name: RO_GSCVD $ - verified that guybrush device boots fine with the new image. Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/guybrush: Add variant_tpm_gpio_tableRob Barnes
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkinKevin Chiu
For Guybrush Board Version 2, Nipperking Board Version 1, update SPKR GPIO to match H/W schematic: SPKR: GPIO31 For Nipperkin Board Version 2, update SPKR GPIO to match H/W schematic: SPKR: GPIO70 BUG=b:202992077 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-16mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_LRob Barnes
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/guybrush/dewatt: update dewatt configChris.Wang
copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-06google/guybrush: Move SPI speed overrideKyösti Mälkki
SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google/guybrush: Set Gen3 default for all PCIe devicesMatt Papageorge
Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-04mb/google/guybrush/bootblock: add comment on selecting eSPI interfaceFelix Held
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02mb/google/guybrush: Update STT coefficientsJason Glenesk
Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-28mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC scale/offset value, it needs to update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 92165 -> 73457 VDD offset: 412 -> 291 SOC scale: 30233 -> 30761 SOC offset: 457 -> 834 BUG=b:200194315 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If53c173000a276a80247ccb08736280a25948939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-27mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3Rob Barnes
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32 for other uses. This move applies to all board except: * Guybrush * Nipperkin board version 1 Add callbacks for variants to override fpmcu shtudown gpio table and fpmcu disable gpio table. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint still works. Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85Karthikeyan Ramasubramanian
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain and save the GPIO_3 in S5 domain for other use-cases. This move applies to all board except: * Guybrush * Nipperkin board version 1 Update the GPIO configuration, device tree configuration accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC <-> TPM communication is working fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Fix GPIO overrides during verstageKarthikeyan Ramasubramanian
GPIO overrides are defined for verstage. But the overrides are neither enabled nor applied during verstage. Enable the overrides and apply them during verstage. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and cold reboot cycling for 10 iterations each. Ensure that all the PCIe devices are enumerated fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Remove WWAN_DISABLE GPIOKarthikeyan Ramasubramanian
In-band controls work to enable/disable the WWAN module. Hence WWAN_DISABLE_GPIO is not critical and can be marked as not connected. BUG=b:188415287 TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is enumerated on boot and reboot. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-27mb/google/guybrush: Update SD_AUX_RESET_L signalKarthikeyan Ramasubramanian
On all upcoming variants and board versions of existing variants, SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all boards except: * All board versions of Guybrush * Nipperkin Board Version 1. Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18. Configure the gpios accordingly in baseboard, guybrush and nipperkin variants accordingly. Also update the DXIO port descriptor for SD PCIe engine with the corresponding AUX reset GPIO. BUG=b:202992077 TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD Controller and SD Card are enumerated fine. Ensure that the enumeration is successful after a suspend/resume cycle. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush: Reconfigure GPIO_5Karthikeyan Ramasubramanian
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On Nipperkin board version 1, pen is not stuffed and instead the GPIO is used to control LCD Privacy settings. On upcoming Nipperkin board versions and other variants, GPIO_5 is not used. Configure GPIO_5 accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush. Ensure that the configuration is retained on existing boards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush/var/nipperkin: config eSPI alert as in-bandKevin Chiu
To prevent unexpected alert from eSPI to SOC, configure this alert pin to in-band. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush/var/nipperkin: Add G2 GTCH7503 HID TS supportKevin Chiu
Follow up the G2 spec: G7500_Datasheet_Ver.1.2 BUG=b:203607764,b:202090378 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I98dd3095043ab537d91e81b84944779240b203ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-25mb/google/guybrush/var/nipperkin: override dxio to turn off WLAN ASPM L1.2/L1.2Kevin Chiu
turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure. BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage AP is able to be probed by wlan module Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storageKevin Chiu
BUG=b:195269555 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage eMMC sku is bootable Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/guybrush/var/nipperkin: Override GPIO configurationKarthikeyan Ramasubramanian
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO DescriptorKarthikeyan Ramasubramanian
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21mb/google/guybrush: Make DXIO Port Descriptor configurableKarthikeyan Ramasubramanian
Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19mb/google/guybrush/dewatt: update DRAM tableKenneth Chan
Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL Hynix LPDDR4X 4266 2G H54G46CYRBX267 Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_ENFelix Held
The definition of those bits changed between Picasso and Renoir/Cezanne so add a comment where those bit definitions are used as well. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15mb/google/guybrush/bootblock: drop redundant clearing of LPC decodesFelix Held
The writes were originally added due to being part of the initialization sequence in the reference code, but coreboot already has those registers cleared by the time we reach this part of the code, so we can drop these redundant writes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43344460e5355664841d77daf1df3fd386e047e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 21:17:53 +0000