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path: root/src/mainboard/google/guybrush
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2022-01-14soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-12mb/google/guybrush/var/dewatt: Update unused GPIO pinsKenneth Chan
According to H/W schematics, fingerprint, SD controller, WWAN/LTE and PEN modules are not stuffed and hence the following GPIOs are marked as not connected: GPIO_3 : TP247 GPIO_4 : TP218 GPIO_5 : TP220 GPIO_8 : TP245 GPIO_11: TP244 GPIO_17: TP194 GPIO_18: TP195 GPIO_21: TP243 GPIO_24: TP196 GPIO_31: TP50 GPIO_42: TP219 GPIO_69: TP217 GPIO_115: TP235 GPIO_116: TP205 GPIO_140: TP226 GPIO_142: TP225 GPIO_144: TP227 BUG=b:204155627 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I552fd6af1cd827e4e41be1a954bf95c3afbb6a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-12mb/google/guybrush/var/dewatt: Support ALC5682I-VS codecKenneth Chan
ALC5682I-VS codec will be used in EVT, replacing ALC5682I-VD. BUG=b:211835769 TEST=emerge-guybrush coreboot chromeos-bootimage; HW reworked a proto MB with ALC5682I-VS, build and check "i2cdetect -r -y 2", dmesg. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ib1a82285b60c6d5d474ead8643a826e36f56f5b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-10src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS
Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: I50fcbb16895662c7451fec1569a8a61398792531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10guybrush: Inject SPDs into APCBRob Barnes
Inject SPDs into APCB at coreboot build time. BUG=b:209486191 BRANCH=None TEST=Boot guybrush and nipperkin with injected APCB Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-06mb/google/guybrush/var/dewatt: update USB3 settings for passing SIKenneth Chan
Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-06mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changedKenneth Chan
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3354766. Update to matched id for audio work normal. 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2. BUG=b:210542422 TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I542f886fe63205777837d7146169177b043cc5f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane ParameterKevin Chiu
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment" per port: port#0: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#1: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#4: COMPDISTUNE0: 0x1->0x6 / TXVREFTUNE0: 0x3->0xE port#5: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 BUG=b:203049656 BRANCH=guybrush TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. pass USB eye diagram verification Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04mb/google/guybrush/var/dewatt: disable unused PCIe clock settingKenneth Chan
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush. Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt. BUG=b:211566312 TEST=emerge-guybrush coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: If449453bc60ed41e104346429babc06a73acef64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-26mb/google/guybrush/var/dewatt: update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt: vdd scale: 95359 vdd offset: 449 soc scale: 31481 soc offset: 193 BUG=b:211566312 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/guybrush/var/dewatt: update DRAM ID tableKenneth Chan
1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL 2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants) BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for ↵Kenneth Chan
USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-20mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGERob Barnes
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-18mb/google/guybrush: Disable GPIO export for Goodix TouchscreenRaul E Rangel
We want ACPI to own the GPIOs. This will stop the GPIOs from being exposed to the OS driver. BUG=b:209705576, b:210694108 TEST=Dump ACPI table and verify GPIO are no longer in _CRS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-17mb/google/guybrush/var/nipperkin: config eSPI as dedicated alertKevin Chiu
Setup eSPI to dedicated alert per the latest schematic changes. DUT won't hang up at power on boot due to eSPI alert is triggerred unexpectedly. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage test power on/reboot on DUT (6 units) each 10 loops->pass Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-16mb/google/guybrush/var/dewatt: Add audio codecKenneth Chan
Add ALC5682I-VD and ALC1019 for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie4d21a11377c73b913a8f79a92d5869ea70f4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-15mb/google/guybrush: Set TPM to to be kernel power managed.Rob Barnes
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause the TPM kernel driver to send a shutdown command before s0i3 entry. This change depends on S0i3 verstage running and reinitializing the TPM. BUG=b:200578885 BRANCH=None TEST=TPM shutdown sent during s0i3 entry on guybrush Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM tableKevin Chiu
add Hynix H54G56CYRBX247 support BUG=b:210365851 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage power on successfully Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13mb/google/guybrush/var/dewatt: Add Elan touchscreenKenneth Chan
Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5) BUG=b:208373433 TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13mb/google/guybrush/var/dewatt: Add Synaptics touchpadKenneth Chan
Add Synaptics S9831 touchpad for dewatt. BUG=b:208182457 TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Configure Smart Card in normal modeKarthikeyan Ramasubramanian
As per the schematics, smart card is expected to operate in normal mode by default. So configure the SOC_SC_PWRSV gpio accordingly. BUG=b:202992077 TEST=Build and boot to OS in Nipperkin board version 2. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-08mb/google/guybrush: Combine mem_parts_used.txtRob Barnes
Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstageKarthikeyan Ramasubramanian
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID straps and Developer Mode Beep signals. During boot up it is LOW and selects RAM_ID straps. When the system enters OS, it is driven HIGH and selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5 domain it does not reset until the system enters mechanical off (G3) state. On scenarios where the power button is pressed when the system is in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still selecting DEV BEEP signal. This causes boot up failures. Fix this by configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage. BUG=b:204450368 TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle followed by a S5 -> S0 boot cycle for 2 iterations successfully. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01guybrush: add RO_GSCVD area to FMAPVadim Bendebury
This area is used for storing AP RO verification information. BRANCH=none BUG=b:141191727 TEST=built a guybrush firmware image and verified that the RO_GSCVD area was indeed added: $ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \ grep -B3 RO_GSCVD area: 25 area_offset: 0x00808000 area_size: 0x00002000 (8192) area_name: RO_GSCVD $ - verified that guybrush device boots fine with the new image. Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/guybrush: Add variant_tpm_gpio_tableRob Barnes
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkinKevin Chiu
For Guybrush Board Version 2, Nipperking Board Version 1, update SPKR GPIO to match H/W schematic: SPKR: GPIO31 For Nipperkin Board Version 2, update SPKR GPIO to match H/W schematic: SPKR: GPIO70 BUG=b:202992077 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-16mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_LRob Barnes
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/guybrush/dewatt: update dewatt configChris.Wang
copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-06google/guybrush: Move SPI speed overrideKyösti Mälkki
SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google/guybrush: Set Gen3 default for all PCIe devicesMatt Papageorge
Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-04mb/google/guybrush/bootblock: add comment on selecting eSPI interfaceFelix Held
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02mb/google/guybrush: Update STT coefficientsJason Glenesk
Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-28mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC scale/offset value, it needs to update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 92165 -> 73457 VDD offset: 412 -> 291 SOC scale: 30233 -> 30761 SOC offset: 457 -> 834 BUG=b:200194315 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If53c173000a276a80247ccb08736280a25948939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-27mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3Rob Barnes
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32 for other uses. This move applies to all board except: * Guybrush * Nipperkin board version 1 Add callbacks for variants to override fpmcu shtudown gpio table and fpmcu disable gpio table. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint still works. Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85Karthikeyan Ramasubramanian
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain and save the GPIO_3 in S5 domain for other use-cases. This move applies to all board except: * Guybrush * Nipperkin board version 1 Update the GPIO configuration, device tree configuration accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC <-> TPM communication is working fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Fix GPIO overrides during verstageKarthikeyan Ramasubramanian
GPIO overrides are defined for verstage. But the overrides are neither enabled nor applied during verstage. Enable the overrides and apply them during verstage. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and cold reboot cycling for 10 iterations each. Ensure that all the PCIe devices are enumerated fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Remove WWAN_DISABLE GPIOKarthikeyan Ramasubramanian
In-band controls work to enable/disable the WWAN module. Hence WWAN_DISABLE_GPIO is not critical and can be marked as not connected. BUG=b:188415287 TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is enumerated on boot and reboot. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-27mb/google/guybrush: Update SD_AUX_RESET_L signalKarthikeyan Ramasubramanian
On all upcoming variants and board versions of existing variants, SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all boards except: * All board versions of Guybrush * Nipperkin Board Version 1. Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18. Configure the gpios accordingly in baseboard, guybrush and nipperkin variants accordingly. Also update the DXIO port descriptor for SD PCIe engine with the corresponding AUX reset GPIO. BUG=b:202992077 TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD Controller and SD Card are enumerated fine. Ensure that the enumeration is successful after a suspend/resume cycle. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush: Reconfigure GPIO_5Karthikeyan Ramasubramanian
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On Nipperkin board version 1, pen is not stuffed and instead the GPIO is used to control LCD Privacy settings. On upcoming Nipperkin board versions and other variants, GPIO_5 is not used. Configure GPIO_5 accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush. Ensure that the configuration is retained on existing boards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush/var/nipperkin: config eSPI alert as in-bandKevin Chiu
To prevent unexpected alert from eSPI to SOC, configure this alert pin to in-band. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush/var/nipperkin: Add G2 GTCH7503 HID TS supportKevin Chiu
Follow up the G2 spec: G7500_Datasheet_Ver.1.2 BUG=b:203607764,b:202090378 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I98dd3095043ab537d91e81b84944779240b203ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-25mb/google/guybrush/var/nipperkin: override dxio to turn off WLAN ASPM L1.2/L1.2Kevin Chiu
turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure. BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage AP is able to be probed by wlan module Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storageKevin Chiu
BUG=b:195269555 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage eMMC sku is bootable Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/guybrush/var/nipperkin: Override GPIO configurationKarthikeyan Ramasubramanian
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO DescriptorKarthikeyan Ramasubramanian
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21mb/google/guybrush: Make DXIO Port Descriptor configurableKarthikeyan Ramasubramanian
Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19mb/google/guybrush/dewatt: update DRAM tableKenneth Chan
Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL Hynix LPDDR4X 4266 2G H54G46CYRBX267 Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_ENFelix Held
The definition of those bits changed between Picasso and Renoir/Cezanne so add a comment where those bit definitions are used as well. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15mb/google/guybrush/bootblock: drop redundant clearing of LPC decodesFelix Held
The writes were originally added due to being part of the initialization sequence in the reference code, but coreboot already has those registers cleared by the time we reach this part of the code, so we can drop these redundant writes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43344460e5355664841d77daf1df3fd386e047e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-14mb/google/guybrush: Fix variant_has_pcie_wwan helperKarthikeyan Ramasubramanian
variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is enabled. On some variants, this engine is used by storage controllers. Fix it by adding a weak override that returns no PCIe WWAN by default. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is enumerated on boards where it is stuffed. Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-14mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3Rob Barnes
S3 is not currently functional on Guybrush. Remove support from ACPI. BUG=b:202401767 b:181766974 TEST=Boot Guybrush Confirm 'deep' is not in /sys/power/mem_sleep Confirm S0ix suspend/resume still works BRANCH=None Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-14mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entryKarthikeyan Ramasubramanian
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on S0i3 entry. Based on the schematics, the pull-down on that signal leads to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to achieve some power savings and de-assert it on S0i3 exit. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the signal gets asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger suspend/resume cycles and ensure that the WWAN module is enumerated after each cycle. Change-Id: I43c8655ee5209779748e4365db973e094cb08aca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/guybrush: Re-arrange override speed configKarthikeyan Ramasubramanian
Currently override speed config is applied only for non EM100 cases. For EM100 case, override speed board version defaults to 0 leading to "comparison of unsigned expression >= 0 is always true" error. Fix this error by defining the override speed config for both EM100 and non-EM100 use-cases. BUG=None TEST=Build Guybrush for both EM100 and non-EM100 cases. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/guybrush: Override SPI Fast speedsKarthikeyan Ramasubramanian
Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13mb/google/guybrush/var/nipperkin: update fw_config fieldKevin Chiu
update fw_config for nipperkin BUG=b:196909635 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Icd2c5509450e70aed158f146179f3a7fa24b547a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-12mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360APatrick Huang
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A" BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Cq-Depend: chromium:3195465 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-11mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO DescriptorMatt Papageorge
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume. BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/guybrush: drop printk in bootblock_mainboard_early_initFelix Held
bootblock_mainboard_early_init gets called before console_init. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF writeFelix Held
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS updateFelix Held
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can remove the clearing of that bit. This is split off from the previous patch to be able to use timeless build to verify that the previous patch didn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11mb/google/guybrush: Use register and bit defines for eSPI setupRaul E Rangel
It's hard to understand what this code is doing because it uses hard coded values, so use the register and bit defines instead. BUG=none TEST=Timeless build for guybrush results in identical binary. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/guybrush: Build chromeos.c in verstageHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds chromeos.c in verstage to call get_ec_is_trusted() in vboot verstage_main(). Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/guybrush: Add GPIO EC in RW to early GPIO tablesHsuan Ting Chen
Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in verstage. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-11mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMeKevin Chiu
nipperkin has different H/W topology to guybrush that the eMMC device is on a different GPP: guybrush: GPP3 nipperkin: GPP2 Hence we need to enable RTD3 for nipperkin additionally which refers to this one: https://review.coreboot.org/c/coreboot/+/54967 BUG=b:200246826 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage run suspend test on eMMC sku Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-24mb/google/guybrush: Remove ALS presentationGwendal Grignou
guybrush does not have a light sensor, do not include ACPI0008 ACPI device (Light sensor that will be managed by acpi-als IIO kernel driver). BUG=b:200823325 TEST=Check on Guybrush360 the sensor is not presented. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-24mb/google/guybrush: Configure the level for AMD Firmware binariesKarthikeyan Ramasubramanian
AMD Firmware tool allows configuring the directory table level in which the binaries have to be added. This helps to achieve space and boot time savings. BUG=b:195329409 TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of ~75 ms and space savings of ~600 KB per RW section. Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23mb/google: Update comments in mem_parts_used.txt to match new templatesReka Norman
BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google: Bulk rename mem_list_variant.txt to mem_parts_used.txtReka Norman
The variant creation script creates a placeholder file called mem_parts_used.txt, with the intent that variant owners will populate this file with memory parts as needed. But instead, some partners have been adding the parts in a new file called mem_list_variant.txt and removing the placeholder file. E.g. https://review.coreboot.org/55735. There's nothing wrong with this, but it's confusing to have two different file names which serve the same purpose. Bulk rename all the mem_list_variant.txt files to mem_parts_used.txt. The only time these file names are used is as an argument to the spd_tools part_id_gen script, so no other changes are necessary. BUG=None TEST=Re-run part_id_gen for all variants of brya/volteer/dedede/guybrush/zork. Check that the only change is to the "Generated by" comment in Makefile.inc and dram_id.generated.txt. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/guybrush: Migrate guybrush to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all guybrush variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for guybrush: util/spd_tools/bin/part_id_gen \ CZN \ lp4x \ src/mainboard/google/guybrush/variants/guybrush/memory \ src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt For dewatt, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/guybrush -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I48ca430b80b892d68dad582b1d9937a9edafa5d4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21mb/google/guybrush: Add placeholder SPD fileReka Norman
BUG=b:191776301 TEST=dewatt build no longer fails when a check for non-existent files in LIB_SPD_DEPS is added (following commit). Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iee0c5e8b71f7cc7c016a38a60569daff99a55027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21mb/google/guybrush: Use open drain eSPI alertsRob Barnes
Remove the override in guybrush devicetree that configured in-band eSPI alerts. This will result in guybrush using dedicated open-drain eSPI alerts. Guybrush boards must be reworked to connect the eSPI alert line, otherwise they will not boot with this change BUG=b:198596430 TEST=Boot on reworked guybrush BRANCH=None Change-Id: I185eec773336fb662d9fe7f4c11991813e4d7cd6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57778 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21mb/google/guybrush: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by adding alias for following devices: 1. FPMCU 2. WWAN Additionally, this change drops the __weak attribute for variant_has_* functions as there is no need for different implementations for the variants. Change-Id: I8af5e27f226270e6b40a50640c87de99a5a703f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/guybrush: Reorganize bootblock_mainboard_early_init()Martin Roth
This now skips all of the pieces done by PSP_verstage. BUG=None TEST=Boot Guybrush with & without PSP_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USBMartin Roth
Since the PCIE training for the USB WWAN card is no longer being run, we can initialize the GPIOs the same for all WWAN cards. BUG=b:193036827 TEST=Boot and reboot with fibocom FM350-GL & L850GL modules Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/guybrush: If not using PCIe WWAN, disable the portMartin Roth
Check to see if the PCIe slot needs to be activated for the WWAN card. If it doesn't, leave it unused so it will be powered off and not do the PCIe training. BUG=b:193036827 TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16mb/google: Unify all variants to start with "-> "Martin Roth
All variants originally had been changed to start with an arrow with two spaces following it to line up with the platform name. A number of recent platforms were added only using a single space. This change updates them all to have two spaces so they line up again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-10mb/google/guybrush: Invert USB descriptions in devicetreeRob Barnes
The USB descriptions are flipped. Fix by inverting the USB descriptions in devicetree. BUG=None TEST=Build BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/guybrush: Document USB mapping in devicetreeRob Barnes
Add a short documenting comment to each usb entry in devicetree so it is clear which function each usb port maps to. BUG=None TEST=Build BRANCH=None Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09mb/google/guybrush/var/nipperkin: Add ELAN TS supportKevin Chiu
ELAN TS: eKT3644 BUG=b:194961444 TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Id1601efbbe419bb28233a2678fdde005a55da671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08soc/amd/cezanne/fsp_m_params: set usb_phy version and length.Julian Schroeder
Setting the usb_phy version and length in the soc code instead of devicetree. That way the devicetree code does not have to reapeat it for different AMD Cezanne based systems. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/guybrush/variants/baseboard/devicetree: update usb_phy versionJulian Schroeder
The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6. If the ID does not match, the FSP USB will not set up the phy. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Cq-Depend: chrome-internal:4087511 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/guybrush: update the telemetry settingIvy Jian
Update the telemetry setting for guybrush vddcrvddfull_scale_current : 94648 #mA ddcrvddoffset : 785 vddcrsocfull_scale_current : 30314 #mA vddcrsocoffset : 560 BUG=b:189157660 TEST=Build Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I19ba3d69be63d0f8491d15ee48ce9ba468a46fdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 08:33:10 +0000