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path: root/src/mainboard/google/guybrush
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2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Unmask eSPI keyboard IRQRaul E Rangel
PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Remove PS/2 mouse configRaul E Rangel
Guybrush doesn't have a PS/2 mouse. BUG=none TEST=boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: PCIe GPIOs - enable enables, disable resetsMartin Roth
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush/port_descriptors: add dummy descriptorsFelix Held
This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptorsMartin Roth
pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/guybrush: add DXIO and DDI descriptorsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-06Revert "mb/google/guybrush: Disable GFX"Raul Rangel
This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-06mb/google/guybrush: Disable GFXRaul E Rangel
This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/guybrush/var/guybrush: Add Codec and Speaker configrationKarthikeyan Ramasubramanian
Enable I2C2 in devicetree and fill ACPI information for Codec and Speaker amplifiers. Pass correct IRQ GPIO for headset jack. BUG=None BRANCH=None TEST=Ensure that the Codec and Speaker Amplifiers are detected in i2cdetect. Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/guybrush: Add Bluetooth configurationKarthikeyan Ramasubramanian
Configure the BT disable GPIO to logic low in order to enable Bluetooth. Add USB ACPI configuration for BT device. BUG=b:182201890 TEST=Build and boot to OS. Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05mb/google/guybrush: Enable camera power GPIOIvy Jian
Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05mb/google/guybrush: Update GPIO configurationMartin Roth
Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mb/google/guybrush: Enable early EC Software SyncKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync is complete. Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-02mb/google/guybrush: Add Elan Touchpad configurationKarthikeyan Ramasubramanian
Enable Touchpad by configuring the enable GPIO to logic high. Add touchpad configuration for ELAN touchpad. BUG=b:182207444 TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events are detected using evtest. Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01mb/google/guybrush: Add IRQ numbersRaul E Rangel
BUG=b:183737011 TEST=cat /proc/interrupts and see i2c controllers and gpio controller listed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b2f23b2c2a7c4cec198276814d80f545e85aa41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-31mb/google/guybrush: Enable VBOOT_LID_SWITCHRaul E Rangel
Needed so get_lid_switch will actually call the EC. Otherwise it returns -1. BUG=b:183524609 TEST=Depthcharge no longer halts complaining that coreboot didn't sample the pin Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-31mb/google/guybrush: Switch eSPI to 16 MHzRaul E Rangel
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16 MHz makes everything a lot more stable. BUG=b:183524609 TEST=Boot to OS and run `ectool version` 1000 times and see no problems. Before with 33 MHz there was an error every few cycles. declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i" Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-03-29mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PINFelix Held
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select it and remove the temporary workaround that was implemented in the mainboard code in commit 39ef89033624a2d14b0c77cdbdf287dd7d7059e1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29mb/google/guybrush: Enable DISABLE_SPI_FLASH_ROM_SHARINGRaul E Rangel
Guybrush uses GPIO67 as an input. BUG=none TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10068bb6870b2cb96033cf3893cde71db5c1d709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51781 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: Temporary fix to set eSPI muxMathew King
This change allows guybrush EC communication while other patches in the SOC code are worked on. BUG=b:183149183 TEST=Boot guybrush with EC comunication Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable PCIe devices in devicetreeMathew King
BUG=b:181690884 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Add guybrush APCBs into buildMartin Roth
This adds the Guybrush APCBs into the AMD firmware binary. BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13mb/google/guybrush: Add ACPI support for Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Configure eSPI GPIOs in early stageMathew King
BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure early GPIOs in earliest stageMathew King
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Enable verstageMathew King
BUG=b:181961514 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-11mb/google/guybrush: Enable USB ports in devicetreeMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/google/guybrush: Enable Chrome EC SKUID and BOARDIDMathew King
BUG=b:181910592 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11mb/google/guybrush: Log mainboard events to elogMathew King
BUG=b:180653357 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/guybrush: Add chomeec device to lpc bridgeMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/guybrush: Add smihandlerMathew King
BUG=b:180507707 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10mb/google/guybrush: Enable Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/guybrush: Enable internal graphicsMathew King
BUG=b:181809122 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I64475a475e9b72a6edd04ce0728591e0649d9f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-03mb/google/guybrush: Add SPDs to build for Guybrush variantMartin Roth
These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/guybrush: Add generated LPDDR4x SPDsMartin Roth
These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-02mb/google/guybrush: Set up FW_CONFIG fieldsMathew King
BUG=b:180523962 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02mb/google/guybrush: Add eSPI configurationMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Add option to toggle GPIO for sign of lifeMathew King
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing. BUG=b:180721202 TEST=builds Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22mb/google/guybrush: Enable console UARTMathew King
BUG=b:180530492 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable guybrush variantMathew King
Enable the building of guybrush variants and configure the first variant also called guybrush. BUG=b:180419462 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable ACPI tablesMathew King
BUG=b:180419454 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-19mb/google/guybrush: Enable CONFIG_CHROMEOSMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/guybrush: Configure non-native function GPIOsMathew King
Second pass GPIO configuration to enable the non-native function GPIOs based on the guybrush Proto 0 reference schematic 0210. BUG=b:177909472 TEST=builds Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-13mb/google/guybrush: Add plain dsdtRaul E Rangel
Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-06mb/google/guybrush: First pass GPIO configuriation for GuybrushMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06mb/google/guybrush: Add stubs to configure GPIOsMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23mb/google/guybrush: Set FWM position to an upper addressZheng Bao
Setting other places causes build error. BUG=b:178241112 TEST=Build Change-Id: I85d5d44c458feed38d69f21f899d6b4380963ec7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-22mb/google/guybrush: Set the ROMSIZE as 16MZheng Bao
Change-Id: Iec8b40bd89c25cd2193aff8af45d0a09b07ad6a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/google/guybrush: Add default FMD file to the buildMathew King
BUG=b:175143925 TEST=builds; binary has correct layout Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I4f3826c8ed0dfd7219eaa5f0cc285f1fe89a4e1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-17mb/google/guybrush: Add new mainboardMathew King
Guybrush is a new Google mainboard with an AMD SOC. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 21:30:29 +0000