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2024-09-01tree: Use boolean for s0ix_enableElyes Haouas
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15mb/google/guybrush: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot guybrush (dewatt) with SMMSTORE enabled. Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30mb/google: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-03-04mb/google/guybrush: turn off SD ASPM L1.1/L1.2JasonNien
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests: L1ss disabled SD plugged power idle test: 735.3875 L1ss enabled SD plugged power idle test: 737.2335 L1ss disabled SD plugged power video test: 333.29325 L1ss enabled SD plugged power video test: 333.442 BUG=b:254382832 TEST=test pass over 10k cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier
Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-27soc/amd: use common ACPI_SCI_IRQ definitionFelix Held
ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17mb/google/guybrush: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot guybrush Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-08Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"Zheng Bao
Updated Linux FW works with PCI gen3 speed and PSPP. This reverts commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed") https://review.coreboot.org/c/coreboot/+/63593 and commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN") https://review.coreboot.org/c/coreboot/+/63722 The changes are overlapped and are reverted together. BUG=b:240426142 & b:228830362 The system is able to ran over 2500 cycles on Nipperkin with command suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \ --nofw_errors_fatal The whole variant_update_dxio_descriptors is empty and is pushed back to weak function. Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-11-02mb/google/guybrush: Set PS2K_IRQ to level/lowMark Hasemeyer
On guybrush, keyboard presses are signaled by the EC via eSPI virtual wire. The interrupt is shared with others and should be active low. From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"): > The default state for the IRQ lines when the eSPI controller comes > out of reset is high. This is because the IRQ lines are shared with > the other IRQ sources using AND gates. This means that in order to > not cause any spurious interrupts or miss any interrupts, the > IO-APIC must use a low polarity trigger. Setting `vw_irq_polarity` in the device tree provides an option to invert interrupts from the eSPI controller, but the register is initialized from verstage which is baked into RO. As a workaround, the necessary interrupts on the EC have been reconfigured to be active low, and we can modify the IO-APIC accordingly. EC related CL here: https://crrev.com/c/4891663 BUG=b:218874489 TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage` -Flash new RW fw and verify keyboard is functional -`suspend_stress_test -c 1` and verify i8042 irq is removed as a wake source -`echo mem > /sys/power/state`. Press key and verify system wake from i8042. Cq-Depend: chromium:4891663 Change-Id: I7d093d94a666263684645ef724e945069c68c806 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-10-28mb/google/guybrush: Clean up Kconfig entriesMatt DeVillier
Alphabetize board entries, Kconfig selections, and config options. Change-Id: I599eda8c136d072471f022be9397faeb0e061472 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28mb/google/guybrush/Kconfig.name: Alphabetize entries, add namesMatt DeVillier
Alphabetize entries and add consumer product names for boards where available. Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25soc/amd/*/Kconfig: rework SPL optionsFelix Held
Move all security patch level (SPL) related Kconfig options to the common AMD PSP Kconfig file. Commit 4ab1db82bb30 ("soc/amd: rework SPL file override and SPL fusing handling") already reworked the SPL handling, but missed that another Kconfig option SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL controlled if the PSP mailbox command to update the SPL fuses was sent by the code that got added to the build when PERFORM_SPL_FUSING was selected. To make things less unexpected, rename PERFORM_SPL_FUSING to SOC_AMD_COMMON_BLOCK_PSP_SPL since it actually controls if the SPL support code is added to the build and also rename SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL to PERFORM_SPL_FUSING. This changes what PERFORM_SPL_FUSING will do from including the code that could do the fusing if another option is set to being the option that controls if the fusing mailbox command will be set. All SoCs that support SPL now select SOC_AMD_COMMON_BLOCK_PSP_SPL in their Kconfig, which won't burn any SPL fuses. The logic in the Skyrim mainboard Kconfig file is reworked to select PERFORM_SPL_FUSING for all boards on which the SPL fuses should be updated; on Guybrush PERFORM_SPL_FUSING default is changed to y for all variants. The option to include the code that checks the SPL fusing conditions and allows sending the command to update the SPL fuses if the corresponding Kconfig is set doesn't need to be added on the mainboard level, since it's already selected at the SoC level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-04soc/amd: rework SPL file override and SPL fusing handlingFelix Held
The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. For this the SPL file needs to be present in the PSP directory table. The SPL version check happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-29mb/google/guybrush: Disable WLAN ASPMTim Van Patten
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be measured with cyclictest: $ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec down to 35-65 usec. These latency spikes can impact the user when real-time processes like Audio (cras) are starved of CPU time, leading to buffer underruns resulting in crackling/distorted audio. ASPM is already disabled for Nipperkin devices (CB:63537), so this CL disables it for both in the shared declaration of guybrush_czn_dxio_descriptors. Power impact for Dewatt: * ASPM enabled power_VideoCall.FDO_25min_webrtc w_energy_rate 7.425043688811071 power_Idle.default20min wh_energy_used 1.4164200000000022 * ASPM disabled power_VideoCall.FDO_25min_webrtc w_energy_rate 8.779998551703423 power_Idle.default20min wh_energy_used 1.4860800000000012 When using Google Meet over WiFi, power increases by ~1.5W. BUG=b:297970318 TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000 Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-25mb/google/guybrush: Use only one option for common selectsFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_BASEBOARD_GUYBRUSH. Thus, move all selects to the latter option. Change-Id: I570c3cfd3d100ad90e35ec5d89686cb6a4bd8e82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/guybrush: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on dewatt, verify unknown device for the ACP machine driver no longer present. Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21mb/google/guybrush: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: If2c9c52f1e2866082df8e534b1a074639bb62db2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75020 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/guybrush: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-14mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki
It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09mb/google/guybrush: Store XHCI resourcesRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 250 | 2022-10-11 16:04:49 | S0ix Enter 251 | 2022-10-11 16:04:53 | S0ix Exit 252 | 2022-10-11 16:04:53 | Wake Source | GPE # | 31 253 | 2022-10-11 16:04:53 | Wake Source | PME - XHCI (USB 2.0 port) | 1 254 | 2022-10-11 16:05:24 | S0ix Enter 255 | 2022-10-11 16:05:27 | S0ix Exit 256 | 2022-10-11 16:05:27 | Wake Source | GPE # | 31 257 | 2022-10-11 16:05:27 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin, verified that XHCI wake events show up in elog Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68326 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-11soc/amd/*: Add SOC_NAME in fw.cfg(s)Zheng Bao
2/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I18f73462a3995038fe93750320dfc053fec969ba Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-22mb/google/guybrush: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all touchpad functions work correctly. Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-13mb/google/guybrush,skyrim: use gpio.h include everywhereFelix Held
Now that gpio.h will only include the defines in the IASL case, gpio.h can be included instead of soc/gpio.h in the files that will be directly or indirectly included in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/guybrush: use gpio.h includeFelix Held
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian
On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-07mb/google/guybrush: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in CB:67779. Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07mb/google/guybrush: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. This mirrors the change to skyrim in CB:67778. BUG=b:121309055 TEST=build/boot guybrush with rest of patch series Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_tableMatt DeVillier
Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename all variant tables and getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/guybrush: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim and Zork. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/google/guybrush,skyrim: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I286557d6ad83990bc101eaa930bde04345859c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/(guybrush|skyrim): Use a variable for APCB filenameMartin Roth
We use the name of the APCB file repeatedly, so put it into a variable so that it's easier to update. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06mb/google/guybrush: Fix SMMSTORE size, alignmentMatt DeVillier
SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build guybrush with SMMSTOREv2 enabled Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30mb/google/guybrush: move EC switch selection from ChromeOS to VbootMatt DeVillier
This is a vboot feature, not a ChromeOS one, and unless selected by vboot, compilation will fail in the non-ChromeOS + vboot build case. TEST=build/boot guybrush w/vboot, w/o ChromeOS Change-Id: I3108bcc8dfeacd99c9f5d36bd915d590292fef00 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67994 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30guybrush: mark RO_GSCVD area unusedHimanshu Sahdev
This area relates to storing of AP RO verification information. CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and guybrush is using TPM_GOOGLE_CR50. Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the RO section up by 8K, they were misaligned. Hence marking this area as unused instead of removing the same to work around ChromeOS infrastructure shortcoming. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30mb/google/guybrush: enable display backlight in ramstageMatt DeVillier
Commit c7204b5a4 [mb/google/guybrush: Enable backlight in the OS] disabled the GPIO for the display backlight in favor of using ACPI to enable it, but this breaks display output for payloads which do not/can not enable the backlight GPIO themselves (edk2, grub, SeaBIOS). Re-enable the GPIO for display backlight so that payloads other than depthcharge work properly. TEST=build/boot google/dewatt with Tianocore payload, verify payload display visible. Change-Id: I2519d779954ed89486045aa7de0b18f1c31a4374 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-27mb/google/guybrush: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the GPIO table comes from the baseboard, and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. Change-Id: Ib8439e664defeafd2d08cffb74c997ab69230231 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier
Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08guybrush: remove RO_GSCVD area from FMAPHimanshu Sahdev
This area relates to storing of AP RO verification information. CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and guybrush is using TPM_GOOGLE_CR50. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com>
2022-09-01mb/google/guybrush: select SYSTEM_TYPE_LAPTOPMatt DeVillier
Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to mobile (vs the default of desktop). TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-30mb/google/nipperkin: Set BT enable_delay_ms to 10msRob Barnes
Override bluetooth enable_delay_ms to 10ms, per advise from vendor. BUG=b:233369179 BRANCH=guybrush TEST=Boot nipperkin, connect to headset, suspend and reboot, headset still functions. Change-Id: Ic00de6704018f27339512929f85531aa72205b0e Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67177 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30mb/google/guybrush: Set BT enable_delay_ms to 200msRob Barnes
Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common denominator between the two BT chipsets. BUG=b:233369179,b:236289478 BRANCH=guybrush TEST=Connect to headset, suspend and reboot, headset still functions Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-15mb/google/guybrush: Pass in Cr50 IRQ to PSPRaul E Rangel
Different guybrush boards have different TPM IRQs. This change passes in the correct GPIO to the TPM. BUG=b:241824257 TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test passes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61954fa4493fd56e528b616ca65166a31917f557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarityRaul E Rangel
The default state for the IRQ lines when the eSPI controller comes out of reset is high. This is because the IRQ lines are shared with the other IRQ sources using AND gates. This means that in order to not cause any spurious interrupts or miss any interrupts, the IO-APIC must use a low polarity trigger. On zork/guybrush/skyrim the eSPI IRQs are currently working as follows: * On power on/resume the eSPI controller drives IRQ 1 high. * eSPI controller gets configured to not invert IRQ 1. * OS configures IO-APIC IRQ 1 as Edge/High. * EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1 high. * eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ 1 as high. This results in missing the first interrupt. * When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the eSPI controller to set IRQ1 to low. We are now primed to catch the next edge high interrupt. This is generally not a problem since the linux driver will probe the 8042 with interrupts off. On S3/S0i3 resume since the eSPI controller comes out of reset driving the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is configured to trigger on edge high. This results in the 8042 controller getting incorrectly marked as a wake trigger. By configuring the IO-APIC to use low polarity interrupts, we no longer lose the first interrupt. This also means we can use a level interrupt to match what the EC actually asserts. We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI because the linux kernel will ignore the level/polarity parameters for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't have this problem. The PIC is not currently configured anywhere and it defaults to an edge/high trigger. We could add some code to configure the PICs trigger register, but I don't think we need the functionality right now. For zork and guybrush, this change is a no-op. eSPI is configured in verstage which is located in RO, and we have already locked RO for these devices. We will need to figure out how to properly set the `vw_irq_polarity` for these devices. BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104 TEST=On zork, guybrush and skyrim $ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count' Verify keyboard works as expected and no interrupt storms are observed. On morphius I verified keyboard and mouse work on windows as well. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-20mainboard/google/guybrush: Update Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel specific functionality that results in it not working properly on AMD platforms. This commit updates the base device tree to use the generic PCIe driver instead. BUG=none TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/google/guybrush: Remove duplicated includeElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I19cd9360a2571e8b88b1ed1005ce8564bdacb297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-23mb/google/guybrush/var/dewatt: Update telemetry valueKenneth Chan
AMD SDLE testing had been done. Apply the following telemetry settings for dewatt DVT: vdd scale: 91573 vdd offset: 620 soc scale: 30829 soc offset: 235 BUG=b:234417498 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Change-Id: I46650ca12ccfec90f15ee562d30c62c389d14d39 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-06-07mb/google/guybrush: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232298307 TEST=None Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07mb/google/guybrush: Remove TODO's and update textJon Murphy
Remove TODO's for dummy DXIO descriptors, update comment to reflect what they are. These devices are needed for the platform to function properly. Also remove the TODO for DDI descriptors as they are functioning correctly. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-25mb/google/guybrush: Remove unused GPIO tableJon Murphy
On Guybrush, the power and lid switches are managed by the EC and coreboot and the AP have no control over them within this context. Remove unused GPIO's to prevent coreboot warnings about resampling at boot. BUG=b:233771033 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-25mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. Missed changes to variant.h in initial commit(already merged) BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-22mb/google/guybrush: Remove TODO for ESPI functionsJon Murphy
The feature request was moved to Skyrim in the interest of time and effort. The bug was updated to reflect this, and the comment should be removed from the monkey island code base BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfigFelix Held
Use the existing definitions from FspUsb.h instead of magic values for the ComboPhyStaticConfig settings in the mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-24mainboard/google: Remove unused <boardid.h>Elyes Haouas
Found using: diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<" Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dewatt: Set SPI speed to 100Mhz on board version 3Rob Barnes
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 BRANCH=guybrush TEST=Build and boot to OS in Dewatt board version 3. Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/nipperkin: Fix WLAN to GEN2 speedRob Barnes
Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing the PSP to hang when resuming from S0ix suspend. The root cause is still under investigation. Just disabling PSPP fixes the hang but causes poor PLT performance. BUG=b:228830362 BRANCH=guybrush TEST=suspend_stress_test on AC and DC Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"Rob Barnes
This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/google/guybrush/var/dewatt: Override SPI fast speedKenneth Chan
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/guybrush/var/dewatt: Update APU STT settingChris.Wang
update STT setting for dewatt. BUG=b:228040295 BRANCH=guybrush TEST=build, verify the parameter has been applied to the system by checking the AGT tool. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-18mb/google/guybrush: Remove EC_ENABLE_LID_SWITCHRob Barnes
Remove EC_ENABLE_LID_SWITCH since this causes a duplicate SW_LID entries. The other SW_LID entry is generated by MKBP. BUG=b:228907256 BRANCH=guybrush TEST=Lid open close triggers events on Nipperkin Change-Id: I5c1cf7aeac8405bce7bfc77110eceaf3e5383fe7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-18mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ssKevin Chiu
BUG=b:227296841 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass PLT criteria: S0 > 600ms, s0i3 > 14 days Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-14mb/google/guybrush: Set BT USB to use GPIO for statusTim Van Patten
Set the BT USB device to use GPIO for the power status. This causes an ACPI `_STA()` function to be generated that returns the power status of the BT USB device, rather than always returning `0x1`. This `_STA()` function can be used during boot to skip enabling the device (and performing the associated sleep) if the device is already powered on. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14mb/google/nipperkin: Disable PSPP for WLANRob Barnes
Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-13mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_configKevin Chiu
BUG=b:228448327 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage check ACPI device "LCD" in SSDT Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-13mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and DewattYu-Hsuan Hsu
We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio values in kernel Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/guybrush: allow MKBP devices and disable TBMC deviceKenneth Chan
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:227240985 BRANCH=guybrush TEST=manual test on Dewatt: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-05mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD dataChris.Wang
The value at offset 329 should be: 0x4B -> "K" not 0x48 -> "H" in ASCII code. BUG=b:224884904 TEST=Build, confirm the part number is matched the corresponding parts Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05mb/google/guybrush/var/dewatt: Override SPD file for Samsung partsRobert Zieba
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This commit overrides the default SPD files used for these parts BUG=b:224884904 TEST=Verified that Dewatt SKU1 and SKU3 boot with changes Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-01mb/google/guybrush: Remove elog_gsmi_cb_mainboard_log_wake_sourceRob Barnes
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. BUG=b:227163985 BRANCH=gubyrush TEST=No 164 errors detected during suspend_stress_test /sys/firmware/log output after resume before change: SMI# #1 ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC Chrome EC: clear events_b mask to 0x0000000000000000 after change: SMI# #6 ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/google/guybrush/var/dewatt: add specific SPD hex for dewattChris.Wang
Add the specific SPD hex file for the Samsung memory part with updating the part number into the SPD table. The ABL needs to identify the part by checking SPD data to do the proper tuning. BUG=b:224884904 TEST=Build, validate the SPD data has been applied. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-30mb/google/guybrush: Disable EN_SPKR on initYu-Hsuan Hsu
We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot guybrush and verify the devbeep and gpio value in kernel Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30mb/google/guybrush/var/dewatt: Update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt EVT: vdd scale: 91288 vdd offset: 279 soc scale: 29785 soc offset: 461 BUG=b:219626910 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Change-Id: I4456ffddbf9963f1202a349abe52df2bbb726468 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63136 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung partsRobert Zieba
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This commit assigns them exclusive IDs 9 and 11 to facilitate this. BUG=b:224884904 Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 73331 -> 94623 VDD offset: 1893 -> 1847 SOC scale: 31955 -> 29904 SOC offset: 852 -> 756 BUG=b:217963719 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18mb/google/guybrush/port_descriptors: use enum values for link speedFelix Held
Use GEN3 from enum dxio_link_speed_cap instead of the number 3. TEST=Timeless build results in identical firmware image for guybrush Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-15mb/google/guybrush/var/nipperkin: update APU STT settingKevin Chiu
BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCKRaul E Rangel
The verstage.c file contains PSP verstage specific code. We don't need it when using x86 verstage. BUG=b:193050286 TEST=Build and boot guybrush with x86 verstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/guybrush: Enable DEBUG_SMI for non-serial firmwareRaul E Rangel
In order to copy the PSP verstage logs into x86 cbmem, we need to enable DEBUG_SMI. This will include the CBMEM console code in SMM. I only enable DEBUG_SMI when UART is disabled because SMM doesn't currently save/restore the UART registers. This will result in clearing the interrupt enable bits and makes it so you can no longer use the TTY. BUG=b:221231786, b:217968734 BRANCH=guybrush TEST=Build serial and non serial firmware and verify DEBUG_SMI is set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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