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2024-10-05mb/google/fatcat/var/fatcat: Rename audio codec optionsSubrata Banik
The new names include the `AUDIO_` prefix to clearly indicate that they are audio-related options. TEST=Able to build google/fatcat w/o any functional impact. Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: change touchscreen fw_config name for THC I2CCliff Huang
use TOUCHSCREEN_THC_I2C instead of TOUCHSCREEN_THC0_I2C BUG=b:348678529 TEST=Able to build google/fatcat Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I689dd72a925c76ca6c2c9a941f4857daae20c943 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84652 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: Add GPIO settingsJeremy Compostella
BUG=b:348678529 TEST=Boot google fatcat board till FSP memory training Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-04mb/google/fatcat/var/fatcat: Add FW_CONFIG for UFC and WFCSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I4061b9b4c1e515e8c078c67f30f29eee87b84a66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84645 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-03mb/google/fatcat: Add Panther Lake SOC supportSaurabh Mishra
- This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-27mb/google/fatcat/var/fatcat: add support for wifi sar tableYH Lin
Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG is used to select different sar table (index 0 to 3). BUG=b:348678529 TEST=emerge-fatcat coreboot chromeos-bootimage Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-09-27mb/google/fatcat/var/fatcat: Add initial FW_CONFIGSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add HDA verb tablesJeremy Compostella
We use ALC256 as HDA codec on fatcat hence, added the verb table. BUG=b:348678529 TEST=Tested audio playback using HDA ALC256 codec on PTL reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add memory settingsJeremy Compostella
BUG=b:348678529 TEST=Memory training is successful on google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-25mainboard/google/fatcat: Update SoC to Panther LakeSubrata Banik
This commit updates the fatcat mainboard to use the Panther Lake SoC instead of Meteor Lake. The changes include: - Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option. - Updating the `mainboard_update_soc_chip_config()` function to use the `soc_intel_pantherlake_config` struct. - Updating the devicetree to use the `soc/intel/pantherlake` chip. - Updating variant header files to reflect the SoC change. This update enables support for the Panther Lake SoC and its features on the fatcat mainboard. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mainboard/google/fatcat: Remove unused virtual GPIOsSubrata Banik
This commit removes the virtual GPIOs for recovery and write protection from the fatcat variant. These GPIOs are not utilized on the fatcat platform, and their removal simplifies the GPIO configuration and improves code readability. The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther Lake SoCs. Future changes will introduce a suitable GPIO device name that meets the requirements of Panther Lake. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for fatcat: DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) BUG=b:347669091 TEST=emerge-fatcat coreboot Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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