diff options
| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2024-09-17 14:52:59 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-10-03 03:37:07 +0000 |
| commit | 362cc976fb498435f94b8d982c33a54b1dd7ab56 (patch) | |
| tree | 11b336f2b95a9dbac5b06ca887a1a112c47e41b0 /src/mainboard/google/fatcat/variants | |
| parent | 6042ba010a181acc94c7d947158bc52184f03d7e (diff) | |
mb/google/fatcat: Add Panther Lake SOC support
- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fatcat/variants')
| -rw-r--r-- | src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb | 64 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h | 2 |
2 files changed, 65 insertions, 1 deletions
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 73b99dbc94..f73cae1f14 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -1,3 +1,65 @@ chip soc/intel/pantherlake - device domain 0 on end + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + + # Enable s0ix + register "s0ix_enable" = "false" + + # DPTF enable + register "dptf_enable" = "false" + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "pch_hda_dsp_enable" = "true" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_sdi_enable" = "{ true, false }" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref npu on end + device ref xhci on end + device ref pmc_shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref soc_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + end end diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h index e468198171..0e937dc0e0 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h +++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h @@ -6,5 +6,7 @@ #include <baseboard/gpio.h> /* TODO: Add GPIO as per fatcat board */ +/* Dummy pin number for ACPI table to build */ +#define GPE_EC_WAKE 0 #endif /* __MAINBOARD_GPIO_H__ */ |