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2022-06-18mb/google/dedede/var/shotzo: Add EC defines for ACPITony Huang
Update Shotzo own ec.h with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. In MAINBOARD_EC_SCI_EVENTS drop following events. EC_HOST_EVENT_LID_OPEN EC_HOST_EVENT_LID_CLOSED EC_HOST_EVENT_BATTERY_LOW EC_HOST_EVENT_BATTERY_CRITICAL EC_HOST_EVENT_BATTERY EC_HOST_EVENT_BATTERY_STATUS set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. In MAINBOARD_EC_S5_WAKE_EVENTS drop below event. EC_HOST_EVENT_LID_OPEN In MAINBOARD_EC_S3_WAKE_EVENTS drop following events. EC_HOST_EVENT_AC_CONNECTED EC_HOST_EVENT_AC_DISCONNECTED EC_HOST_EVENT_KEY_PRESSED EC_HOST_EVENT_KEY_PRESSED BUG=b:235303242 BRANCH=dedede TEST=Build Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/dedede/var/shotzo: Generate SPD ID for supported partsTony Huang
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: - MT53E512M32D2NP-046 WT:E - H9HCNNNBKMMLXR-NEE - K4U6E3S4AA-MGCR - MT53E512M32D1NP-046 WT:B - H54G46CYRBX267 - K4U6E3S4AB-MGCL - K4U6E3S4AA-MGCL BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com>
2022-06-13mb/google/dedede/beadrix: Update SoC gpio pin of I2C cameraTeddy Shih
Update SoC GPIO setting of unused I2C camera pins according to beadrix schematics. GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA) GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL) BRANCH=dedede BUG=b:235005592 TEST=on beadrix, validated by beadrix's camera still working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/dedede/beadrix: Update probe daughter LTE mainboard SARTeddy Shih
Update FW_CONFIG probe for daughter board LTE and mainboard SAR according to beadrix schematics. BRANCH=dedede BUG=b:226910787, b:213549229, b:233983127 TEST=on beadrix, validated by beadrix LTE working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09mb/google/dedede/var/shotzo: Deselect BASEBOARD_DEDEDE_LAPTOPTony Huang
Shotzo is not a laptop (it is a Chromebase), therefore deselect BASEBOARD_DEDEDE_LAPTOP. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/dedede: Create shotzo variantTony Huang
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-06-01mb/google/dedede/beadrix: Add fw_config probe for ALC5682-VD & VSTeddy Shih
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BRANCH=dedede BUG=b:226910787,b:232057623 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2022-05-20mb/google/dedede/beadrix: Update FW_CONFIG probe for daughter board LTETeddy Shih
To make sure daughter board LTE existing, we update probe to DB ports value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11) as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14) BRANCH=dedede BUG=b:226910787 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I9ab4412b614ec665fbafc998756b805591982b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-19mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE ↵Teddy Shih
suspend To make sure Realtek RTL8822CE suspend stress test smoothly, we remove 1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12), as well as, remove redundant 17.0 and 1c.6 that both are described by baseboard/devicetree.cb BRANCH=dedede BUG=b:230386474 TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress test properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-05-17mainboard/**/devicetree.cb: Fix typoAngel Pons
repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16mb/{google,ocp}: Remove unused <bootstate.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-05mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SARTeddy Shih
To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects EC of I2C 5 bus and GPIO D22, D23, as well as, SoC of GPIO E11, refer to mainboard schematic. BUG=b:213549229 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: If172d13aa62503547227adf91f049ea50b948888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/dedede/beadrix: Update DPTF settingTeddy Shih
Update DPTF Policy and temperature sensor values from thermal team. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27soc/intel/jasperlake: Revert CdClock settingSimon Yang
Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-24mainboard/google: Remove unused <boardid.h>Elyes Haouas
Found using: diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<" Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia. BUG=b:223687184 TEST=emerge-dedede coreboot Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power ↵Teddy Shih
consumption To achieve low power consumption, we disable unused PCIe and SATA pins at beadrix/overridetree.cb according to baseboard/devicetree.cb and mainboard schematic. Original measured beadrix board's power consumption is about 250 mW. After we disable unused PCIe and SATA pins, as well as, enable the other low power MUX CL (3487086: USB MUX: Update low power mode of MUX anx7447 used as MUX only | https://chromium-review.googlesource.com/c/chromiumos/platform/ec/ +/3487086), the measured power consumption achieves about 110 ~ 116 mW, as well as, meets Google battery life for 14 days in the suspend state and Intel low power consumption about 116 mW. BRANCH=dedede BUG=b:204882915 TEST=on beadrix, measured power consumption meets Intel power consumption. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776 Reviewed-by: Teddy Shih <teddyshihau@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG optionTeddy Shih
Enable/disable LTE function based on LTE field of FW_CONFIG. 1. GPIO control 2. USB port setting BUG=b:213582491 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-19mb/google/dedede/var/lantis: Add ELAN touchscreen support for LandridRobert Chen
The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller. BUG=b:222976965 TEST=emerge-dedede coreboot Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-18mb/google/dedede/var/galtic: update Wifi SAR for for galnatFrank Chu
Add wifi sar for galnat/galnat360 Use SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) galnat (sku id:0x140000)* gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) galnat360 (sku id:0x2B0000)* BUG=b:222008376 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I868a7416a002732736cabea48ce80548ea75e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreenFrank Chu
For galnat platform, support 2nd ELAN touchscreen via SSFC. Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8) for touchscreen controller switch. BUG=b:221002826 TEST=touch screen is functional. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-14mb/google/dedede: Update DPTF settingTeddy Shih
Update PL1, PL2, and temperature sensor values from thermal team, as well as, we remove unused temperature sensors according to baseboard/devicetree.cb and mainboard schematic. After we check DTT setting, the thermal and performance test pass. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, run following commands: localhost /tmp # cat /sys/class/thermal/thermal_zone*/type x86_pkg_temp INT3400 Thermal TSR0 TSR1 TCPU localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp 45000 20000 32800 32800 39000 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07drivers/tpm/spi: Refactor out some cr50-specific logicTim Wawrzynczak
Mainboards accessing the cr50 over an I2C bus may want to reuse some of the same firmware version and BOARD_CFG logic, therefore refactor this logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses the new tis_vendor_read/write() functions in order to access the cr50 regardless of the bus which is physically used. In order to leave SPI devices intact, the tis_vendor_* functions are added to the SPI driver. BUG=b:202246591 TEST=boot to OS on google/dratini, see the same FW version and board_cfg console prints as before the change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-28mb/google/dedede/var/pirika: Add Wifi SAR for pasaraFrank Chu
Add wifi sar for pasara BUG=b:216411442 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-15mb/google/dedede/var/beadrix: Add LTE power off sequenceTeddy Shih
This change adds LTE power off sequence for beadrix. BUG=b:204882915 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: I11370bf69438465d2230e2633044ba42685a152b Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61329 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12mb/google/dedede/var/beadrix: Add LTE modem supportTeddy Shih
This change adds LTE modem for beadrix. BUG=b:204882915 BRANCH=dedede TEST=Build and boot beadrix, check with command modem status Change-Id: I7acb88634478ff486810b2c3fc14d6739c3268e1 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61328 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-10mb/google/dedede/var/magolor: Add custom Wifi SAR for magnetoTyler Wang
Add wifi sar for magneto. Due to fw-config cannot distinguish between magolor and magneto. Using sku_id to decide to load magneto custom wifi sar. BUG=b:208261420 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-02-01mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCRFrankChu
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AA-MGCR BUG=b:214460184 TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHzFrankChu
Galtic has a rare stability issue. The symptom is display black screen while switching to secure mode, normally it will occurred at the last step of factory side and it'll follow by some specific SOCs. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommend for short term solution for Gal series. The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for Galtic. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCMVarshit B Pandya
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO from the PCH. The current power sequence does not take this into account, and this leads to an unbalanced ref count of the reset GPIO, which can cause one or the other of the devices to reset unexpectedly. This patch corrects that by explicitly sequencing the reset GPIO for both devices, which the builtin refcounting of this driver will automatically handle. BUG=b:214665783 TEST=Build, boot to OS and check VCM once camera stream off Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHzDavid Wu
When using the default initial core display clock frequency, Metaknight has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for metaknight. BUG=None BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-19mb/google/dedede/var/bugzzy: Add SAR sensorSeunghwan Kim
Present the Semtech SX9360 SAR sensor that protects the LTE antenna. The sensor is connected to i2c bus I2C1. BUG=b:194318328 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59609 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHzSeunghwan Kim
When using the default initial core display clock frequency (648MHz), Jasper Lake board might have a rare stability issue where the startup of Chrome OS in secure mode may hang during re-initializing display in kernel graphic driver. Bugzzy didn't show this problem so far, but Intel recommends slowing the initial core display clock frequency down to 172.8 MHz to prevent this potential problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for bugzzy. BUG=None BRANCH=dedede TEST=Build firmware and check the DUTs can boot up in secure mode well. Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17Revert "mb/google/dedede/var/beadrix: Remove SD controller"Teddy Shih
This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5. Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. ================ error log ================ ... Starting depthcharge on Beadrix... src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5. =========================================== BUG=b:204882915 BRANCH=None TEST=Build and boot into OS. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/dedede/var/beadrix: Add memory part and generate DRAM IDTeddy Shih
This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60242 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-12mb/google/dedede/var/beadrix: Configure GPIO settingsTeddy Shih
Override GPIO pad configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-12mb/google/dedede/var/beadrix: Correct memory settingsTeddy Shih
Based on the beadrix's schematic, generate memory settings. BUG=b:204882915, b:210123929 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60244 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-10src/mainboard/google: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07mb/google/dedede/var/boten: Add Wifi SAR for bookemStanley Wu
Add new sku id apply for bookem wifi sar table. BUG=b:211705077 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I1e5bac662fb44cf631ae1453068dec898b6e2607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-05mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screenSeunghwan Kim
Touch screen IC couldn't wake up after rebind with current 120 ms delay after reset since the HID would be activated after 200 ms from reset. This change increases the reset_delay_ms for touch device to 200 ms to wait for the touch HID to be ready. BUG=b:204950000 BRANCH=dedede TEST=Verified that TSP IC could wake up after rebind Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCRZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for Samsung K4U6E3S4AA-MGCR. BUG=b:211950312 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2022-01-03mb/google/dedede/var/bugzzy: Initialize display signals on user modeSeunghwan Kim
Bugzzy uses panel-built-in touch screen, it needs to set panel power and reset signal to high for touch screen to work. On user mode, coreboot doesn't initialize graphics since there is no screen display before OS. So we would add a WA to initialize required signals on user mode. It takes under 30 ms delay on booting time. BUG=b:205496327 BRANCH=dedede TEST=Verified touch screen worked with test coreboot and test touch screen 028D firmware Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-01mb/google/dedede/var/magolor: Set core display clock to 172.8 MHzRen Kuo
When using the default initial core display clock frequency, Magolor has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for magolor. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/dedede/var/magolor: Add stylus functionRen Kuo
Add the stylus field in fw_config. Update devicetree and gpio to handle stylus pen detection. BUG=b:167983049 TEST=Build firmware and check behavior as following: 1) Set the fw_config "bit4=1" for pen present: Wake up from suspend when pen is removed from the garage. Present the stylus menu when pen is removed from the garage. 2) Set the fw_config "bit4=0" for pen absent: Wake up and present menu will not work when pen is removed form the garage. Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/google/dedede/var/beadrix: Remove SD controllerTeddy Shih
Remove SD controller configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/google/dedede/var/beadrix: Add internal USB camera supportTeddy Shih
This change adds internal USB camera into devicetree for beadrix. BUG=b:204882915, b:210772511 BRANCH=None TEST=Built and checked camera device existence with lsusb Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable audio featureTeddy Shih
This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix. BUG=b:204882915, b:210756131 BRANCH=None TEST=Built and heared speaker sound on OS Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable PIXA touchpadTeddy Shih
This change adds PIXA touchpad into devicetree for beadrix. BUG=b:204882915, b:203113111 TEST=Built and verified touchpad function Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/cret: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:203837656 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15mb/google/dedede/var/madoo: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Micron MT53E512M32D1NP-046 WT:B 2. Samsung K4U6E3S4AB-MGCL 3. Hynix H54G46CYRBX267 BUG=b:209889645 BRANCH=dedede TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13mb/google/dedede/var/lantis: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:206676530 TEST=build Change-Id: Ie73dc376078c0836edd980e09629399c5cc19594 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/dedede/var/magolor: Add fw_config probe for multi codec andTyler Wang
amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:208912135 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Samsung K4U6E3S4AA-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/dedede: Create beadrix variantTeddy Shih
Create the beadrix variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:204882915 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BEADRIX Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-30mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetleywizard
BUG=b:207307897 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2021-11-22mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDsSeunghwan Kim
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-11mb/google/dedede/var/galtic: update Wifi SAR for convertiblesFrankChu
Add wifi sar for galtic/galtic360/galith360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) BUG=b:203741126 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/google/dedede/var/metaknight: Probe and enable amplifier operation modeDavid Wu
Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=none BRANCH=dedede TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Adjust I2C speedSeunghwan Kim
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns and fall_time_ns values for each port are capured by a scope. BUG=None BRANCH=dedede TEST=built and verified adjusted I2C speed < 400KHz Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/magolor: Enable ELAN touchscreen for magnetoTyler Wang
Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Update charger performance control tableSeunghwan Kim
Update charger performance control table of DPTF for bugzzy. Since the EC change chromium:197776876 modified maximum charging current to reduce skin temperature, this change adjusts the charging performance table with the modified value. BUG=b:197776876 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Enable Wifi SARSeunghwan Kim
BUG=None BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot chromeos-bootimage Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google: Add OEM product names for various boardsMartin Roth
All of these names came from public sources. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-01mb/google/dedede/var/storo: Add fw_config probe for multi audio codecZhi Li
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:202463494 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01mb/google/dedede/var/kracko: Add Wifi SAR for krackoRobertChen
Add wifi sar for kracko BUG=b:194460420 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-27mb/google/dedede/var/lantis: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015941 TEST=run part_id_gen to generate SPD id Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-10-27mb/google/dedede/var/driblee: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL 2. H54G46CYRBX267 BUG=b:204023388 BRANCH=firmware-keeby-14119.B TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/dedede/var/haboki: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Micron MT53E512M32D1NP-046 WT:B Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015944 TEST=run part_id_gen to generate SPD id Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-26mb/google/dedede/var/blipper: Add fw_config probe for multi audio codecYongkun Yu
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:197694580 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com> Change-Id: I422f206b8f1f3705a65808041f1a1544c461b431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/dedede/var/bugzzy: Add LTE power off sequenceSeunghwan Kim
This change adds LTE power off sequence for bugzzy. BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIGSeunghwan Kim
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG. - GPIO control - USB port setting BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I91183f33b92569dd49967ef866d58043d79c287b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/dedede/var/corori: Configure I2C times for TouchpadIan Feng
Configure I2C high / low time in the device tree to ensure Touchpad I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: Touch Pad CLK: 389.2 KHz BUG=b:202787528 TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Change-Id: I0f9d062fc611de0062a39849aee1174268391682 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-15mb/google/dedede/var/sasukette: Add PIXA2635 touchpadZhi Li
Add PIXA touchpad into devicetree for sasukette. BUG=b:202796169 BRANCH=dedede TEST=built sasukette firmware and verified touchpad function Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I5bc8353692a753ec9254ab02b4ff0481386624b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-12mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCLZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=b:202480992 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198713670 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Iaba136a836b89f42411474ae733380e345cce687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11mb/google/dedede/var/pirika: Add Synaptics I2C touchpad deviceAlex1 Kao
Add Synaptics touchpad device support in devicetree. BUG=b:201043984 BRANCH=dedede TEST=Touchpad device function is OK Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS supportIan Feng
Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2021-10-07mb/google/dedede/var/bugzzy: Update GPP_D5 configurationSeunghwan Kim
As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Doan <edoan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-01mb/google/dedede/var/bugzzy: Update device treeSeunghwan Kim
Update bugzzy device tree override based on the EVT schematics. BUG=b:195215785 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/dedede: Remove drawcia_legacy board supportKarthikeyan Ramasubramanian
Support for drawcia_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 22:30:30 +0000