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Add wifi sar for magneto.
Due to fw-config cannot distinguish between magolor and magneto.
Using sku_id to decide to load magneto custom wifi sar.
BUG=b:208261420
TEST= emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AA-MGCR
BUG=b:214460184
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Galtic has a rare stability issue.
The symptom is display black screen while switching to secure mode,
normally it will occurred at the last step of factory side
and it'll follow by some specific SOCs.
Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommend for short term solution for Gal series.
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for Galtic.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`.
Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99
Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
1) If _PRS is present, must have _CRS and _SRS
2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
4) If _SRS is present, probably should have a _DIS (Remark only)
IASL will issue a warning for each missing dependency.
Ignore this warnings for existing ASL code and issue a message when the build is complete.
Change-Id: I28b437194f08232727623009372327fec15215dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Drawcia's MIPI camera sensor and VCM both share the same reset GPIO
from the PCH. The current power sequence does not take this into
account, and this leads to an unbalanced ref count of the reset GPIO,
which can cause one or the other of the devices to reset unexpectedly.
This patch corrects that by explicitly sequencing the reset GPIO for
both devices, which the builtin refcounting of this driver will
automatically handle.
BUG=b:214665783
TEST=Build, boot to OS and check VCM once camera stream off
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When using the default initial core display clock frequency, Metaknight
has a rare stability issue where the startup of Chrome OS in secure mode
may hang. Slowing the initial core display clock frequency down to
172.8 MHz as per Intel recommendation avoids this problem.
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for metaknight.
BUG=None
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Present the Semtech SX9360 SAR sensor that protects the LTE antenna.
The sensor is connected to i2c bus I2C1.
BUG=b:194318328
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59609
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.
Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.
BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.
Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5.
Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
================ error log ================
...
Starting depthcharge on Beadrix...
src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5.
===========================================
BUG=b:204882915
BRANCH=None
TEST=Build and boot into OS.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds memory part used by variant beadrix to
mem_part_used.txt and generates DRAM ID allocated to the part.
BUG=b:204882915, b:210123929
BRANCH=None
TEST=Run part_id_gen to generate SPD id
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60242
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Override GPIO pad configurations based on the beadrix's schematic.
BUG=b:204882915
BRANCH=None
TEST=Built test coreboot image
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I53fc8088ff8ebb2790ac8cd68186cf9de908b414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Based on the beadrix's schematic, generate memory settings.
BUG=b:204882915, b:210123929
BRANCH=None
TEST=Built test coreboot image
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I935581fbf21be4820b03a608ea5bd60b1c000baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60244
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add new sku id apply for bookem wifi sar table.
BUG=b:211705077
TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I1e5bac662fb44cf631ae1453068dec898b6e2607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Touch screen IC couldn't wake up after rebind with current 120 ms delay
after reset since the HID would be activated after 200 ms from reset.
This change increases the reset_delay_ms for touch device to 200 ms to
wait for the touch HID to be ready.
BUG=b:204950000
BRANCH=dedede
TEST=Verified that TSP IC could wake up after rebind
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AA-MGCR.
BUG=b:211950312
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
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Bugzzy uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.
BUG=b:205496327
BRANCH=dedede
TEST=Verified touch screen worked with test coreboot
and test touch screen 028D firmware
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When using the default initial core display clock frequency, Magolor has
a rare stability issue where the startup of Chrome OS in secure mode may
hang. Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommendation avoids this problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for magolor.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Run the command below to fix all occurrences.
$ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,'
Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add the stylus field in fw_config.
Update devicetree and gpio to handle stylus pen detection.
BUG=b:167983049
TEST=Build firmware and check behavior as following:
1) Set the fw_config "bit4=1" for pen present:
Wake up from suspend when pen is removed from the garage.
Present the stylus menu when pen is removed from the garage.
2) Set the fw_config "bit4=0" for pen absent:
Wake up and present menu will not work when pen is removed
form the garage.
Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove SD controller configurations based on the beadrix's schematic.
BUG=b:204882915
BRANCH=None
TEST=Built test coreboot image
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds internal USB camera into devicetree for beadrix.
BUG=b:204882915, b:210772511
BRANCH=None
TEST=Built and checked camera device existence with lsusb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix.
BUG=b:204882915, b:210756131
BRANCH=None
TEST=Built and heared speaker sound on OS
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds PIXA touchpad into devicetree for beadrix.
BUG=b:204882915, b:203113111
TEST=Built and verified touchpad function
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:203837656
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267
BUG=b:209889645
BRANCH=dedede
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:206676530
TEST=build
Change-Id: Ie73dc376078c0836edd980e09629399c5cc19594
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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amplifier
Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB"
BUG=b:208912135
TEST=ALC5682I-VD and ALC1015Q-VB can work normally
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Samsung K4U6E3S4AA-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the beadrix variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:204882915
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEADRIX
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:207307897
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e
Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
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Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:207046230
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add wifi sar for galtic/galtic360/galith360
Using convertible mode of SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
BUG=b:203741126
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Probe the fw_config for RT1015 speaker amplifier operation mode and
enable it accordingly in the device tree.
BUG=none
BRANCH=dedede
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns
and fall_time_ns values for each port are capured by a scope.
BUG=None
BRANCH=dedede
TEST=built and verified adjusted I2C speed < 400KHz
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add ELAN touchscreen support for magneto.
BUG=b:203122673
TEST=Build and verify that touchscreen works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.
BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=None
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All of these names came from public sources.
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"
BUG=b:202463494
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add wifi sar for kracko
BUG=b:194460420
TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage
Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015941
TEST=run part_id_gen to generate SPD id
Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
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Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. H54G46CYRBX267
BUG=b:204023388
BRANCH=firmware-keeby-14119.B
TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Micron MT53E512M32D1NP-046 WT:B
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015944
TEST=run part_id_gen to generate SPD id
Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"
BUG=b:197694580
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally
Signed-off-by: Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
Change-Id: I422f206b8f1f3705a65808041f1a1544c461b431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds LTE power off sequence for bugzzy.
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable/disable LTE function based on DB_PORTS field of FW_CONFIG.
- GPIO control
- USB port setting
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I91183f33b92569dd49967ef866d58043d79c287b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This reverts commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert: This CL did not handle Intel GPIO correctly. We need
to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel
SoC.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure I2C high / low time in the device tree to ensure Touchpad
I2C CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
Touch Pad CLK: 389.2 KHz
BUG=b:202787528
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Change-Id: I0f9d062fc611de0062a39849aee1174268391682
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add PIXA touchpad into devicetree for sasukette.
BUG=b:202796169
BRANCH=dedede
TEST=built sasukette firmware and verified touchpad function
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I5bc8353692a753ec9254ab02b4ff0481386624b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:198713670
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Iaba136a836b89f42411474ae733380e345cce687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Synaptics touchpad device support in devicetree.
BUG=b:201043984
BRANCH=dedede
TEST=Touchpad device function is OK
Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add ALC5682-VS codec support in corori.
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of ssfc.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:201372531, b:194436265
TEST=ALC5682-VD/ALC5682-VS audio codec can work.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2f3edb0b594066714b42050a411103a215e68b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
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As we checked the panel doesn't display firmware screen if we hold
GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
uses the built-in touch screen on the panel, the panel seems like
under reset state by the TOUCHSCREEN_RESET signal.
This change sets default GPP_D5 level to high for bugzzy.
BUG=b:None
BRANCH=dedede
TEST=built and verified bugzzy showed firmware screen
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update bugzzy device tree override based on the EVT schematics.
BUG=b:195215785
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:193694180
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Support for drawcia_legacy board is cancelled. Hence remove the board
support.
BUG=b:192256341
TEST=None
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
|
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Support for Boten_legacy board is cancelled. Hence remove the board
support.
BUG=b:192256341
TEST=None
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
|
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Wheelie variant board has been cancelled. Remove wheelie variant board
support.
BUG=b:192256341
TEST=None
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
|
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Cappy variant is cancelled. Hence delete the cappy variant support.
BUG=b:192256341
TEST=None
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
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Add wifi sar for magma.
Due to fw-config cannot distinguish between magolor and magma.
Using sku_id to decide to load magma custom wifi sar.
BUG=b:192423859
TEST= emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Update PL1 min and max values to 6 W for Galith/Gallop systems.
BUG=b:201010771
BRANCH=None
TEST=Build and verify on Galith/Gallop system
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected.
BUG=b:187482019
BRANCH=dedede
TEST=Built and tested on dedede system
Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add the relevant memory configuration of beetley to the blipper coreboot code
The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267
BUG=b:200000608
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I0b04f64cb007a58ae98f5ed187feb4859a43b1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57670
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add DA7219 codec support in maglet.
BUG=b:198239769, b:196193562
TEST:emerge coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I52d980ed611b3fbe4892cd3e65e3b35931feaba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
BUG=b:191776301
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The variant creation script creates a placeholder file called
mem_parts_used.txt, with the intent that variant owners will populate
this file with memory parts as needed. But instead, some partners have
been adding the parts in a new file called mem_list_variant.txt and
removing the placeholder file. E.g. https://review.coreboot.org/55735.
There's nothing wrong with this, but it's confusing to have two
different file names which serve the same purpose. Bulk rename all the
mem_list_variant.txt files to mem_parts_used.txt. The only time these
file names are used is as an argument to the spd_tools part_id_gen
script, so no other changes are necessary.
BUG=None
TEST=Re-run part_id_gen for all variants of
brya/volteer/dedede/guybrush/zork. Check that the only change is to the
"Generated by" comment in Makefile.inc and dram_id.generated.txt.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all dedede variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for cret:
util/spd_tools/bin/part_id_gen \
JSL \
lp4x \
src/mainboard/google/dedede/variants/cret/memory \
src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt
For cappy, the Makefile.inc was manually modified to use the new
placeholder value.
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/dedede -a -x --timeless
Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Currently, trying to regenerate the galtic Makefile.inc and
dram_id.generated.txt using part_id_gen fails due to duplicate fixed IDs
in the mem_parts_used.txt file.
Remove the fixed IDs since they aren't needed. The part IDs assigned are
the same either way.
Also delete the comments from mem_parts_used.txt, since lp4x/gen_part_id
currently doesn't support comments.
BUG=b:191776301
Regenerate the Makefile.inc and dram_id.generated.txt using gen_part_id,
and check that the part IDs don't changed. Command used:
util/spd_tools/lp4x/gen_part_id \
src/soc/intel/jasperlake/spd \
src/mainboard/google/dedede/variants/galtic/memory \
src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ida83814b2f19b4a56eb9fde5939fa6c7874803c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
On some dedede variants, USB port 2.3/3.3 might be connected to either
LTE device or Type-A external port depending upon FW_CONFIG. Commit
856b579 ("mb/google/dedede/var/kracko: Update LTE USB port
configuration") enabled Type-A external port by default in override
tree and updated the config dynamically for LTE USB device if
FW_CONFIG indicated support for it. This was required because sconfig
lacked the support for multiple override devices. Commit
b9c22e0 ("util/sconfig: Compare probe conditions for override device
match") fixed this behavior in sconfig and now we can add multiple
override devices using different FW_CONFIG probe statements in
override tree. Hence, this change moves the LTE USB device to override
tree for metaknight, kracko and drawcia variants.
In addition to that, drawcia needs to be update reset_gpio depending
upon board_id. Thus, alias `lte_usb2` is used in drawcia override tree
to fix the reset_gpio for older boards i.e. board_id <= 9.
Change-Id: Ie5b205594680d9c2b8543c5c99325d95620cafd2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
On sasukette, codec device might be either 10EC5682 or RTL5682
depending upon the provisioned FW_CONFIG value for
AUDIO_CODEC_SOURCE. The HID for the device was updated in ramstage.c
because sconfig lacked the support for multiple override
devices. Commit b9c22e0 ("util/sconfig: Compare probe conditions for
override device match") fixed this behavior in sconfig and now we can
add multiple override devices using different FW_CONFIG probe
statements in override tree. Hence, this change moves the codec device
to override tree and drops the special handling in ramstage.c
This change also probes for UNPROVISIONED value of FW_CONFIG for
"10EC5682" device since some devices might have shipped with
UNPROVISIONED value and using "10EC5682" device.
Change-Id: I909a29c3df0cbb7ac3c07ca7663a49ad47007232
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update DPTF parameters from internal thermal team.
BUG=b:197546694
BRANCH=dedede
TEST=emerge-keeby coreboot
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I71a76a4d94a704aef7b3cefa2fca3009eb765bb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57693
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: If8b75f9ed4d789d6c9c4365c517358df8d6e55c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Add PIXA touchpad into devicetree for cappy2.
BUG=b:193099842
BRANCH=dedede
TEST=built cappy2 firmware and verified touchpad function
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I840a3ffbaaaac39eaf13bf77e203f6dffdddd3f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This change adds fine-tuned USB2 PHY parameters for cappy2.
BUG=b:199485217
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I2aac29e8bba0bf3eff91898ded7561b6211af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390kHz
codec:395.8kHz
BUG=b:199481261
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ifadc3d19eb57fe6f67504be154c30df7bc0fee71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
All variants originally had been changed to start with an arrow with
two spaces following it to line up with the platform name. A number
of recent platforms were added only using a single space. This change
updates them all to have two spaces so they line up again.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Buggzy's panel is oriented with its "right" side facing upwards, therefore
the firmware screens in depthcharge were incorrectly rotated. This patch
changes the orientation of the framebuffer provided by the FSP.
BUG=b:194967458
BRANCH=dedede
Change-Id: I4a5fbfcfc1c362da1bddd23c7d132416db3691c9
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AA-MGCR (Samsung)
BUG=b:192521391
BRANCH=dedede
TEST=Build and boot bugzzy board
Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
ALC5682-VD/ALC5682-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:193694180
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for this part.
MT53E512M32D1NP-046 WT:B
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ic9ccee7c0957119a69ee179854cf13d30db40621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update DPTF parameters from internal thermal team and Intel suggestion.
BUG=b:198249129
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Based on commit b9c22e09 (util/sconfig: Compare probe conditions for override device match), add fw_config probe for ALC5682I-VS headphone Audio Codec.
BUG=b:197546020
BRANCH=dedede
TEST=ALC5682I-VD/VS and CS42l42 work normally according fw_config
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Iac09663b095e758f1bc0cfaf7adb6e84d203788a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57105
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Roughly half the boards had a "title" comment for the board. This adds
it for the rest of the boards to make everything consistent.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
Touchpad: 386.7kHz
Touchscreen: 387.4kHz
Audio: 385.7kHz
P-sensor: 378.1kHz
BaUG=b:197247706
BRANCH=dedede
TEST=Build and check I2C clock is under 400kHz
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add MT53E512M32D1NP-046 WT:B supported memory part in the
mem_parts_used.txt and generate the SPD ID for the part. Manufacturer
is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech
on MT53E512M32D2NP-046.
BUG=b:194223174
BRANCH=dedede
TEST=Build the gooey board.
Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Drawper change LTE reset pin from GPP_H0 to GPP_H17 from DVT phase.
BUG=b:198117092
TEST=emerge-dedede coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
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Override DdiPortAConfig as MIPI DSI
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board
Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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