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2020-10-26Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"Karthikeyan Ramasubramanian
This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc. CB:45857 overrides the GPIO PM configuration if Cr50 does not support long interrupt pulse width. More recent Cr50 Firmware versions support long pulse width and hence the GPIO PM can take the default configuration. BUG=None TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of suspend/resume sequence, warm and cold reboot cycles each are successful. Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/dedede: Add mainboard acpi support for GPIO PM configurationAamir Bohra
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on low power mode entry and disables it on exit. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:153847814 TEST=Verify S0ix is working. GPIO PM configuration is upadated on low power mode entry and exit. Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>