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Enable USB Port A on daughterboard for Taeko
BUG=b:216533764
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1a43c256757f3fc4b53ba1f794587d6a00ba0aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Enable RTD3 driver for PCIe-eMMC bridge
2. Add fw_config entries for boot device.
BUG=b:211362308
TEST=Build and boot into eMMC storage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic9ef372fa963b040c5196aaf13f2ffde27c168d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nivviks P1 will also use Micron MT62F512M32D2DR-031 WT:B. Add it to the
parts list and regenerate the memory IDs using part_id_gen.
BUG=b:217095281
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Add WiFi SAR table for taeko.
BUG=b:212405459
TEST=build FW and checked SAR table can load by WiFi driver.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I061dc798ae7177d05bc50648cfda46a3eec2c912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM
features from RTD3.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change adjusts I2C3 speed to lower then 400KHz.
BUG=b:215095284
BRANCH=None
TEST=built and verified adjusted I2C3 speed < 400KHz
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ief6773bc37931a5393b5b1b8beaeda61d235f133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:201818726
TEST=build FW and system power on.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I881ded944530b21d1c5e306089d32387c9c258b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Fill in devicetree for nissa baseboard based on schematics.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
TEST=abuild -a -x -c max -p none -t google/brya -b nereid
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The CNVi Wifi controller is considered an untrusted device for ChromeOS,
therefore enable the new UntrustedDevice property for the cnvi_wifi
device on all brya & brask boards.
BUG=b:215424986
TEST=dump SSDT on google/redrix, verify it contains the expected
UntrustedDevice property
Change-Id: Ieff6eea0865125a7c0f626e1981dda1c9532ebb1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ib49164cf51965228c65c6566b0711ae690b6cb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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In the nivviks and nereid pre-proto builds, the memory straps used
don't match those generated by spd_tools. Each pre-proto build only
supports a single memory part, and each of these parts should have ID 0
(see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code
the memory IDs to 0 instead of reading them from the memory strap pins.
From P1 onwards, the memory straps will be assigned based on the IDs
generated by spd_tools.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add a mem_parts_used.txt for each of nivviks and nereid, containing the
memory parts used in their pre-proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.
nivviks:
Micron MT62F1G32D4DR-031 WT:B
nereid:
Samsung K3LKBKB0BM-MGCP
BUG=b:197479026
TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom
contains an spd.bin.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I322a94569d8a63e8c0da68a8feb394ade4ce7999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Fill in the memory config based on the the schematic and doc #573387.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the
related ACPI code. Therefore, move this behind a Kconfig which is
currently selected by the brya and brask baseboards.
BUG=b:197479026
TEST=Build brya0, check that there's no change to the generated dsdt.asl
Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Fill in the nissa baseboard GPIO table based on the nivviks P0 and
nereid P0 schematics. Also, add an override GPIO table for each of
nivviks and nereid.
The differences between nivviks and nereid are:
- WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the
MIPI-related pins are overriden to NC on nereid.
- The DMIC pins and speaker I2S pins were swapped after nivviks P0. The
baseboard reflects the new configuration, which will be used in
nivviks P1 onwards, nereid, and future variants. For now, nivviks
overrides the pins to the old configuration. Once nivviks P1 is
released, this will need to be updated to handle both.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch enables SaGv since somehow it was accidently removed
by commit a52b9c3.
BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya
variants to baseboards")
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch removes `lockable_brya_gpios` lists and
`mb_gpio_lock_config` override function from brya baseboard directory as
the variant GPIO pad configuration table is now capable of locking GPIO
PADs.
BUG=b:208827718
TEST=Able to built and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This applies a configuration lock to the FPMCU SPI and IRQ GPIOs
for all brya and brask variants.
BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests `FPMCU_*`
(F11-F13 and F15-F16) are locked.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This applies a configuration lock to the PCH write protect GPIO for
all brya and brask variants.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This applies a configuration lock to the TPM IRQ pins for all brya
and brask variants.
BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests
GSC_PCH_INT_ODL is locked.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This applies a configuration lock to the TPM I2C and IRQ GPIO for
all brya and brask variants.
BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests
I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use PAD config macro to add lock support for all the gpios used
in CB:58352 CB:58353.
BUG=b:211573253
TEST=Boot to OS, issue warm reboot and see no issue with any IP
enumeration
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`.
Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99
Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Based on the agah schematic, add memory settings.
BUG=b:215662929
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib45241d708d025ca75ed06e2bcf3997558723a62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Create the crota variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:215443524
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CROTA
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To timely update stylus charging status (b:206012072), PCHG device
events have been moved to MKBP. This patch registers the MKPB host
event as a wake-up signal to match the change.
EC filters other EC_MKBP_EVENT_* events (chromium:3413180).
BUG=b:205675485,b:206012072
Cq-Depend: chromium:3413180
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie4536b2c0ccc37f92dfa940c5a5712340a32c82c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
1) If _PRS is present, must have _CRS and _SRS
2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
4) If _SRS is present, probably should have a _DIS (Remark only)
IASL will issue a warning for each missing dependency.
Ignore this warnings for existing ASL code and issue a message when the build is complete.
Change-Id: I28b437194f08232727623009372327fec15215dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is intended for Chrome microchip ECs
only, which have different requirements as to the amount of memory
mapped space they can claim. The brya family of boards does not use
any microchip ECs, therefore remove this Kconfig.
BUG=b:214460174
TEST=boot brya4es to kernel, no EC errors seen in cbmem log, EC software
sync still works.
Change-Id: I6e9858f29d079140ec43341de90f222b03986edb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Some SKUs of google/taniks have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:215487382
TEST=Build FW and checking SD card reader register is correct.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I34adb122bd2edc343e894a53bc12e105f4225984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Init basic override devicetree based on schematics
BUG=b:211891086
TEST=FW_NAME="volmar" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I40b364e3df2f04a6b828f4f288667b96b6e0bd22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:214890058
BRANCH=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I86acb172ed427d45973b9360e0413978cbd46645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8.
According to the latest schematics, Brask supports D3-Hot for RTL8125
and does not need to operate the ISOLATE pin.
BUG=b:193750191
BRANCH=None
TEST=emerge-brask coreboot chromeos-bootimage
Test with command suspend_stress_test
Change-Id: Ica6bfb810887861f6b17ff527373824547e2406c
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set register "reset_delay_ms" to 20 to reduce power resume time.
BUG=b:204009580
TEST=tested on kano
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0695edd7c342c65df9138b1590281c5f442769b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update DPTF settings provided by thermal team
BUG=b:215033682
TEST=build and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Taniks is going to exchange i2c port for touchscreen and cr50.
BUG=b:215039999
TEST=emerge-brya coreboot
Cq-Depend:chromium:3397562
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I179949887f6d8f4bbdff7d806319e2ac368ebc2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Taniks will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.
BUG=b:215040000
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.
Cq-Depend:chromium:3397561
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Enable EC keyboard backlight for volmar.
BUG=b:211891086
TEST=FW_NAME=volmar emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24ec7c8ca770cb438aabcf16b252032eef6d734d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
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Update initial gpio configuration for volmar
BUG=b:211891086
TEST=FW_NAME=volmar emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1bd3f1b3807b546d5a827ac89f0dc9bc8aaec40a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
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Add I2C bus for banshee in Kconfig
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I67592051b367d5a5715f8d1253ea0c11d2deb1c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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Update override devicetree based on schematics
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I05b63ebcded2f37dfb0f6c428e1fb993f476006a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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Change-Id: I624dd67b6ce9b87a6031b5467eacb9a8d7cda1cd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Modify i2c signal to meet touchpad vendor spec.
Please see issue tracker for more details.
BUG=b:215487482
TEST=emerge-brya coreboot and check measured waveform in spec
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib3797d4e232654ada97092d9f2742ca040d0f0e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.
BUG=b:210772498
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Camera LED blinks as sensor is being probed during kernel boot,
which misleads user to belive camera has been turned on.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:214155527
TEST=Build and boot Kano to OS. Verify entries in SSDT and monitor LED
during boot.
Signed-off-by: Jim Lai <jim.lai@intel.com>
Change-Id: I92f1e88d0fcce49660a95d4402c8c4161e320168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61109
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Configure GPIOs according to schematics
BUG=b:214871796
TEST=emerge-brya coreboot
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Id6862ff442310953b4749cef7880814f3c3f6d60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Banshee will use SODIMM. Add memory.c to override baseboard.
BUG=b:208910227
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I4d2fe986b786b3553b67910b589fce12647ee69a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
MEMORY_SOLDERDOWN puts SPD in cbfs and read part number from CBI.
MEMORY_SODIMM puts SPD cache in FMAP.
BUG=b:208910227
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idab48293fb5b584ecb4c8f270d2c376456954553
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Create the banshee variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:214871796
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_BANSHEE
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ib4f943a109f945204a9b0a8de9b99580bf01c87e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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Add file gpio.c in romstage.
BUG=b:213828931
TEST=Build FW and system can power on normally.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie868fe7ada9deb8918d6c7ba538332cbe539ee44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
turns on I2C1 and turns off I2C3.
BUG=b:211886429
TEST=Test if proto 1 can boot into Chrome OS successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I0e94c900b48adf10880aae2abb47e08d1bd9e19b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
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Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some SKUs of google/taeko4es have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:204343849
TEST=Build FW and checking SD card reader register is correct.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I3d2ea3db9df38e7b0cac4c32e1fca579ff43e5bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Configure GPIOs according to schematics
BUG=b:210970640
TEST=emerge-brya coreboot
Change-Id: Icfd1e09761e51aca9c23f3ab340adac7a66a3ada
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Adding this host event to the EC SCI event and wake masks allows
the system to generate an SCI and/or wake when this event happens.
BUG=b:206012072
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4f48244a4fca750a9de2ecc20f24786034d45b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The redrix thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.
BUG=b:200134784
TEST=build and verified by thermal team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The anahera thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.
BUG=b:214088543
TEST=build and verified by thermal team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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After kernel change landed on Chromium tree.
https://lore.kernel.org/r/20210407065555.88110-5-heikki.krogerus@linux.intel.com
USB driver will use PLD to match the Type-C port. PLD needs to start
from 1.
BUG=b:214460183
TEST=boot into OS without kernel panic.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1493e46f8881b2f688f41f32755d4cf5a87e7656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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https://github.com/thesofproject/linux/pull/3271
Felwinter will use the OEM string for SOF tplg loading. Update the name
that match to the kernel driver.
BUG=b:210061842
TEST=dmidecode can show AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib6114d047762ba26071c9cdc6c43d80f933c1eb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61070
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference
Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband
RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and
ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables
CNVI DDR RFIM feature for brya0 variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:201724512
BRANCH=None
TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem
and prefetch mem.
BUG=b:206739931
TEST=build PASS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Init basic override devicetree based on initial schematics
BUG=b:210970640
TEST=emerge-brya coreboot
Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch adjusts CSE region's internal partitions' (CSE RO and Data
partition) sizes to match with sizes of MFIT generated CSE Region's
internal partitions.
BUG=b:213993778
TEST=Generate coreboot for Brya and verify with MFIT generated
coreboot.
Cq-Depend: chrome-internal:4452789
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch ensures all brya variants with Alder Lake ESx SoC
are using NEM by default for CAR set up.
Default CAR configuration for QS SoC is eNEM.
BUG=b:168820083
TEST=Able to build and boot brya0 variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008.
BUG=b:214010928
TEST=touch screen is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to avoid having the FSP fail to detect the SSD device
downstream of the RP, its PERST# must be deasserted earlier in
the boot flow, therefore move PERST# deassertion to a romstage
GPIO table.
BUG=b:213828931
TEST=Build FW and run stress exceed 1000 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The factory versions (minor version 22) of cr50 FW have an issue with
producing short interrupt pulses, which can be missed by the ADL PCH
if autonomous GPIO power management is enabled, therefore instead of
continually adding the setting to all the variants, move it to the
baseboard instead.
Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
MT53E512M32D1NP-046 WT:B (Micron)
MT53E1G32D2NP-046 WT:B (Micron)
H54G46CYRBX267 (Hynix)
H54G56CYRBX247 (Hynix)
K4U6E3S4AB-MGCL (Samsung)
K4UBE3D4AB-MGCL (Samsung)
BUG=none
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic5b45ec83d0d7e0e1d16cb1afae501f06ee1f36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Copy the `is_descriptor_writeable()` function from the `intel/adlrvp`
mainboard and use it in the `configure_pmc_descriptor()` function. With
this change, this function is now identical for both mainboards.
Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
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Adjust the cosmetics of the `configure_pmc_descriptor()` function to
match the code for the `intel/adlrvp` mainboard. The only difference
is that adlrvp checks if the descriptor is writable.
Tested with BUILD_TIMELESS=1, Google Brya0 remains identical.
Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
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Restructure the code in the `configure_pmc_descriptor()` so that it
matches the code for the `intel/adlrvp` mainboard. This change does
not reindent the contents of the original if-block intentionally as
this will be taken care of in a reproducible follow-up.
Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
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More Brya variants like Brya0 and Taeko have migrated to use
Alder Lake QS SoC which enables eNEM feature by default. Hence,
select eNEM for CAR by default for these variants.
BUG=b:168820083
TEST=Able to build and boot brya0 variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update all the ADL-P 15W/28W/45W SKU's PL and PsysPL. These config
values are generated iPDG application with ADL-P platform package
tool. RDC Kit ID for the iPDG tools:
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.
BUG=b:211365920
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable SaGv support for vell
BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: I01e3da449e2cf53278f625ca265d09f7a1869ef7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Create the volmar variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:213127419
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_VOLMAR
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Move memory Makefile.inc and dram_id.generated.txt to correct path
BUG=b:210970640
TEST=emerge-brya coreboot
Change-Id: Ib5d9d9dd6f881f0b9cf2736809a74e5045c3c217
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Felwinter selects DRIVERS_GENESYSLOGIC_GL9755 Kconfig to make use of
SD card reader driver.
BUG=b:209501017
TEST=build PASS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I196ae9c5dbbcc6057d17605eece27563bcc79af8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60893
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add OVTI8856 information for vell:
BUG=b:210801553
TEST=Build and boot on vell
Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:210572663
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Taniks only uses 4 channel speakers. Change the probe name to match
SOF topology settings.
BUG=b:207808510
TEST=dmidecode -t 11 shows correct audio fw_config.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2986bd212cef47f70dfeedc642a8db3314c947f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Tune the I2c frequency
I2C0 - 391 kHz
I2C1 - 391 Khz
I2C2 - 393 kHz
I2C3 - 394.7 KHz
I2C5 - 399.6 KHz
BUG=b:213298209
TEST=build
Change-Id: Id15c5298f8917bac404026f1ecb000fa7f925416
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Fine tune i2c frequency.
I2C0 - 399.6 kHz
I2C1 - 391.4 kHz
I2C3 - 398.1 kHz
I2C5 - 399.9 kHz
BUG=b:213295817
TEST=build
Change-Id: I9a89820a8d9ae4c9b4ee499e8467426e0670656d
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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According to the latest schematic, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:212465011
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Correct the WWAN power sequence to meet spec
BUG=b:213021172
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Iab221fd03c637c82f6ce5c8278d432decf1b30c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:213021171
TEST=FW_NAME=redrix emerge-brya coreboot
Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
moves the TPM I2C setting from the board layer to the baseboard and
fixes the TPM I2C bus assignment.
BUG=b:211886429
TEST=build pass
Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy
screen device), add the same _HID to the privacy screen device.
Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Do initial memory support for project agah
BUG=b:210970640
TEST=FW_NAME=agah emerge-brya coreboot
Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Create the agah variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:210970640
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_AGAH
Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since fw config fields for DB_SD can share the same driver, we will
remove the duplicate fields DB_SD_GL9750 and DB_SD_RTS5232S.
BUG=b:212240358
TEST=emerge-brya coreboot and can boot to OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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After checking them against schematics, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B2 => non-use
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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