diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-01-17 15:56:53 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 14:46:00 +0000 |
| commit | 2bff1545985c9ada3adc78c23ddee259c17b4847 (patch) | |
| tree | bf020f5663e4eac0061ae36706c91b5d2d376d07 /src/mainboard/google/brya | |
| parent | d87b0c371eaebafab4fbf925178cb47480d8b0df (diff) | |
mb/google/brya/var/brask: set tcc_offset value to 10℃
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:214890058
BRANCH=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I86acb172ed427d45973b9360e0413978cbd46645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index a36c849779..466f08a21f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,6 +17,8 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Enable CNVi BT register "CnviBtCore" = "true" |