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path: root/src/mainboard/google/brya
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2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/taeko: Update the FIVR configurationsKevin Chang
This patch sets the enable the external voltage rails since taeko board have V1p05 and Vnn bypass rails. BRANCH=None BUG=b:204832954 TEST=FW_NAME=Check in FSP log and run PLT test Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/brya/var/felwinter: Correct typeC EC mux portEric Lai
Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google/brya/var/kano: Update GPIO table for speak and dmicDavid Wu
Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"David Wu
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. BUG=b:201266532 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/brya: Correct AT24 NVM address sizeVarshit B Pandya
Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02mb/google/brask: add the mkbp deviceZhuohao Lee
In order to let the ec passing the key event like recovery and power key to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP device. BUG=b:204519353, b:204512547 BRANCH=None TEST=pressed recovery key and power button in the OS and checked the UI behavior. Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya/var/brya0: add HPS as generic I2C peripheralDan Callaghan
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for braskDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya/var/taeko: Add probe for MAX98357+ALC5682I_VSJoey Peng
Add probe function for the "VS" version of the audio amplifier so taeko can recgonize MAX98357 with ALC5682I_VS. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize MAX98357 with ALC5682I_VS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-10-29mb/google/brya/var/brask: Correct the GPIO config of buzzerAlan Huang
GPP_B14 is used by buzzer and should be set to NF1 'SPKR'. BUG=b:198998974 TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/anahera: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: disabled autonomous GPIO power managementDavid Wu
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201266532 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: Add fw_config probe for MIPI cameraDavid Wu
Add fw_config probe for MIPI OVTI2740 camera BUG=b:194926283 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5a7cebf1f5c847c01e951a237af691e0ad6c73d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28mb/google/brya/var/taeko: add HPS as generic I2C peripheralDan Callaghan
BUG=b:202784200 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I400719d762b001811f809f9549fd030dff9928d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brya/var/gimble: disabled autonomous GPIO power managementMark Hsieh
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:200918380 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27mb/google/brya/var/kano: Disable unused PCIE root port in devicetreeDavid Wu
The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use these. Having them enabled will occasionally cause suspend attempts to fail, therefore disable them in the overridetree. BUG=b:203389490 b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 settingDavid Wu
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brya/var/kano: Update the FIVR configurationsDavid Wu
This patch set disables the external voltage rails since kano board doesn't have V1p05 and Vnn bypass rails implemented. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25mb/google/brya/variants/gimble: Enable Bluetooth offload supportMac Chiang
Enable CnviBtAudioOffload UPD BUG=b:199180746 TEST=emerge-byra coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 settingDavid Wu
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:202913826 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/brya/var/brask: Correct SSD power sequenceDavid Wu
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21mb/google/brya/var/kano: Enable BT offload supportDavid Wu
Enable the CnviBtAudioOffload UPD and program the corresponding BT VPGIOs. BUG=b:202913826 TEST=emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/var/redrix: Enable bt_offload supportMac Chiang
Enable CnviBtAudioOffload UPD and program the corresponding VGPIO pins BUG=b:191931762 TEST=emerge-coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I81bae537d52592e878db56343970de6fc488950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Add two thermal sensor settingWisley Chen
Anahera has 4 thermal sensors, so add the missing sensors settings. BUG=b:203187535 TEST=build and verified by thermal team. Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Update HID to MX98360AWisley Chen
Because of a change in the chromium OS kernel machine driver for the MAX98357A, a _HID that matches MAX98360A has to be used. (https://chromium- review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/) BUG=b:200778066 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ic68373920d9135e614ff792149079de451ec6e60 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/taeko: enable DPTF functionality for taekoKevin Chang
Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-20mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMCWisley Chen
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6 BUG=b:197850509 TEST=build and boot into eMMC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VSJoey Peng
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID. Update the _HID depending on the AUDIO field of fw_config.Define fw config bit 5-7 in coreboot for codec. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya/var/kano: Correct SSD power sequenceDavid Wu
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:192137970 TEST=FW_NAME=kano emerge-brya coreboot and boot to OS. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_BFurquan Shaikh
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region in case of firmware update. Ensure that the size of the regions match so that we do not have situations where ME_RW_A/B firmware grows bigger than what CSE_RW can hold. BUG=b:189177538 Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: I4da677da2e24b0398d04786e71490611db635ead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-16mb/google/brya/var/taeko: Add fw_config probe for GL9750 and RTS5232SJoey Peng
Add support for SD card reader GL9750 and RTS5232S BUG=b:203014989 TEST=FW_NAME=taeko emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4353a094e2035ce94b5dd1a737e7e7009ad0614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-16mb/google/brya/variants/primus: To fine tune WWAN power sequencingAriel Fang
Follow the spec to correct the WWAN poweron and powerdown sequences. BUG=b:195625346 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15mb/google/brya/var/taeko: Include driver for GL9763E for eMMC boot diskKevin.Chang
Support GL9763E as a eMMC boot disk BRANCH=none BUG=b:202192686 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taeko. Cq-Depend: chromium:3153210 Signed-off-by: Kevin.Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I5db2b229ce1bbea54efe15f5288f13f8d4656899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/brya/variants/brask: Init overridetreeAlan Huang
Init overridetree based on the schematics. Refer to brya0/overridetree.cb to update the settings of the devices including DPTF, WIFI, NAU8825 and etc. Refer to kano/overridetree.cb to update the SSD settings (pcie4_0). TODO: DPTF and USB positions will be further updated later. BUG=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAMEWisley Chen
Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name. BUG=b:197076844 TEST=build and check SSDT. Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-08mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tablesTim Wawrzynczak
Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-10-07mb/google/brya: Disable unused i2s pins for BT offloadSugnan Prabhu S
BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07mb/google/brya: Add PsysPmax setting to 145WRyan Lin
This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04mb/*/brya/variants/brask: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brask to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04mb/google/brya/variants/kano: Correct MIPI camera infoLai, Jim
Correct OVTI2740 information for Kano: MIPI camera CIO port, HID and Link Freq BUG=b:200974074 TEST=Build and boot on Kano camera driver is not probed before, and it can now be probed properly after this change. Signed-off-by: Lai, Jim <jim.lai@intel.com> Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask/var/brask: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for brask BUG=b:197385770 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58041 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya/var/felwinter: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6David Wu
Update GPIO GPP_B5 and GPP_B6 based on schematics. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01mb/google/brya/var/kano: Add Synaptics touchpadDavid Wu
Add Synaptics touchpad for kano. BUG=None TEST=emerge-brya coreboot and check touchpad function work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/google/brya/variants/gimble: Correct SSD power sequenceMark Hsieh
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:201512872 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu
Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29mb/google/brya: Update PCH power cycle related durationsTim Wawrzynczak
The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-28mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_tableKevin Chang
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that taeko can successfully boot into OS with non-serial coreboot. BUG=b:199969366 & b:200711149 TEST=Build FW and test with non-serial FW reboot 20 times pass. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/brya/primus: modify HID to MX98360A for next build phaseMalik_Hsu
For the next build phase, modify the HID of the speaker amp to MX98360A. BUG=b:199098681 BRANCH=none TEST=build coreboot without error Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya/var/kano: Move max98373 amp ACPI info to I2C0David Wu
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya: Correct SSD power sequenceEric Lai
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199822704 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/variants/primus: config dram speed to 3733Casper Chang
This change config the DRAM speed to 3733 for primus. BUG=b:200752480 BRANCH=none TEST=Verified that `dmidecode -t17` shows the correct configured memory speed Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/taeko: Enable SaGv supportJoey Peng
Enable SaGv support for taeko BUG=b:198548214 TEST=FW_NAME=taeko emerge-brya coreboot Flash fw into DUT and can boot successfully Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I580a12ca511d8cde6fee1079e39e6976202da4d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Set vGPIO configurationDavid Wu
Due to the vGPIO is not set correctly, without setting those pins for PEG60, CPU cannot communicate with PCH about the clkreq state. BUG=b:200886824 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6adf73103ecb02c67d9a199e13d2ead9b8b2276f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for kano. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7f56b92b60cadf72eb02fd8bcb87baf36acc16e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Enable SaGv supportDavid Wu
Enable SaGv support for kano BUG=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifc537a5137f5e6eb10cd4c160923ea4da1f6b0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya/variants/gimble: Update DPTF sensorsMark Hsieh
Add two thermal sensors for fan and charger for DPTF based thermal control. BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1529dd5dff3445dd499ed665386a9b06d67c7028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57833 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google/brya/variants/gimble: Update audio settingMark Hsieh
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb BUG=b:197701952 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google: Bulk rename mem_list_variant.txt to mem_parts_used.txtReka Norman
The variant creation script creates a placeholder file called mem_parts_used.txt, with the intent that variant owners will populate this file with memory parts as needed. But instead, some partners have been adding the parts in a new file called mem_list_variant.txt and removing the placeholder file. E.g. https://review.coreboot.org/55735. There's nothing wrong with this, but it's confusing to have two different file names which serve the same purpose. Bulk rename all the mem_list_variant.txt files to mem_parts_used.txt. The only time these file names are used is as an argument to the spd_tools part_id_gen script, so no other changes are necessary. BUG=None TEST=Re-run part_id_gen for all variants of brya/volteer/dedede/guybrush/zork. Check that the only change is to the "Generated by" comment in Makefile.inc and dram_id.generated.txt. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/brya/var/anahera: Update gpio and devicetreeWisley Chen
Based on latest shcematic to update the device tree and gpio. BUG=b:197850509 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I0a999de479c7b2e4776a57e1e56b1568450ec31a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya/var/taeko: Correct IOM port configurationJoey Peng
Enable programming of Type-C AUX DC bias GPIOs. BUG=b:199833078 TEST=Verify that a Type-C monitor works when connected in both orientations. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4f6d80a9f2fc8cdc93226d6c234b54e5db830d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22mb/google/brya/var/redrix: Update audio settingWisley Chen
Update codec/amp setting. 1. Update hid for ALC5682VS 2. Add maxim properties. BUG=b:197076844 TEST=build and check SSDT Change-Id: I8bedd4d0737caf46769ad27bce1768c225ce8a82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22mb/google/brya/var/redrix: Correct SSD power sequenceWisley Chen
The current power sequencing for the SSD does not work in a non-serial enabled BIOS image. It appears that the FSP scans the PCIe RPs before the SSD has time to prepare itself for PCIe, so the FSP disables the RP and so depthcharge cannot find a boot disk. Changing the power sequence timing to enable power in bootblock and deassert reset in ramstage follows the SSD's power sequence and allows it to be discovered by the FSP so the RP does not get disabled. BUG=b:199714453 TEST=build, boot into SSD, and run reboot stress test. Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya: Switch to using device pointers using alias namesFurquan Shaikh
This change replaces the device tree walks with device pointers by adding alias for dptf_policy generic device in the tree. Change-Id: I8fd5476a9cea84ab8b2678167b3e0504eecacf6c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya/var/redrix: Enable EC keyboard backlightWisley Chen
Enable EC keyboard backlight for redrix. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I175d8b91b37c6645ab1a7f05fc6915b3b016e3ff Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya/var/redrix: Get wifi sar nameWisley Chen
Add get_wifi_sar_cbfs_file_name() to return the wifi SAR file name BUG=None TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I87e7a30619fd93d0eae692c4c540c29850ff6721 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya: Add CHROMEOS_WIFI_SARWisley Chen
Add CHROMEOS_WIFI_SAR to include the SAR configs. BUG=None TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I50a413f3425d0b0e0b5ce71dabf6b9477800795e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya/var/felwinter: Configurate AUX pin for USB3 MBEric Lai
USB3 MB doesn't have re-timer. Thus we have to configurate the AUX pin. For now, we use USB3 DB to determine the USB3 MB. BUG=b:197907500 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ide45c77e0a6f736a02d5dc9ad05aa1ef9e754fa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya/var/redrix: Update thermal table.Wisley Chen
Update thermal setting from thermal team. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya/primus: add NVMe power and reset pin to early_gpio_tableMalik_Hsu
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that primus can successfully boot into OS with non-serial coreboot. BUG=b:199967106 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I9c66efe96515347502d059556052c764c1be5d09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya/var/redrix: Enable USB4 PCIe resourcesWisley Chen
Enable USB4 PCIe resources for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I759618055b1282653d8a05fa66e8cdab0c43e3a6 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya: Add WWAN poweroff sequenceEric Lai
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8. BUG=b:180166408,b:187691798 TEST=measure WWAN power off by scope is meeting the spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya/variants/gimble: Add fw_config probe for ALC5682-VD/ALC5682-VSMark Hsieh
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:200009010 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya/variants/kano: Add MIPI camera supportDavid Wu
Add MIPI camera support for OVTI2740 BUG=b:196937374 b:194926283 TEST=Build and boot on Kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Add fw_config probe for eKT3764/eKT3644Wisley Chen
Report different ACPI device depending on TP_SOURCE field of fw config (SSFC-bit8~bit9) for elan touchpad. BUG=b:199503876 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I15781c2d942d81e11c296ea2f2586ba82f67e4a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Select camera module based on SSFC valueArec Kao
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG. BUG=b:198235323 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya: Fix brya0 WWAN poweron sequencingTim Wawrzynczak
The PCIe WWAN module used on brya0 requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage BUG=b:187691798 Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-16mb/google/brya: Update state of BB_RT_FORCE_PWR gpiosTim Wawrzynczak
This GPIO is used to force the USB retimers on Type-C ports to stay in a powered state and can be used e.g., during a firmware update to the retimer to force power on even when no device may be connected to the port. However, its power rail is controlled elsewhere and coreboot is not applying a FW update, so this GPIO should be driven low instead. BUG=b:193402306 TEST=compile Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-16mb/google: Unify all variants to start with "-> "Martin Roth
All variants originally had been changed to start with an arrow with two spaces following it to line up with the platform name. A number of recent platforms were added only using a single space. This change updates them all to have two spaces so they line up again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16mb/google/brya/var/redrix: Add privacy screenWisley Chen
Add privacy screen support. BUG=b:198188272 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ied9d9138f68ba45c4d746aed1cd3f828d4ab7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/57289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15mb/google/brya/variants/gimble: update fw_config for next build phaseMark Hsieh
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/google/brya/var/felwinter: Add R4/R5 for dmicEric Lai
Based on latest schematic (0903) update the GPIO table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15mb/google/brya: Add support for romstage GPIO tableTim Wawrzynczak
Some variants may require more complex power sequencing than can be accomodated with just 2 GPIO tables, therefore introduce one in romstage as well. BUG=b:187691798 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-15mb/google/brya: Enable USB4 PCIe resources for kanoDavid Wu
Enable USB4 PCIe resources for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec914db6914116ebc914a2ba9ff67344b202926b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15brya/gimble: add `get_wifi_sar_cbfs_filename()` in variant.cMark Hsieh
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex BUG=b:189068477 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-11mb/google/brya: Replace white space with tabSubrata Banik
This patch unifies line indentation. Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09mb/google/brya/variants/kano: Update GPIOs config for kanoDavid Wu
Update the GPIO configuration to match the latest schematic. BUG=b:192370253 BRANCH=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I96be95a127f42b005d97a3c02650af13419524a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/primus: update for next build phaseMalik_Hsu
According to the schematic diagram of version C14_MB_20210902A_SB, modify the settings of GPIO and fw_config. BUG=b:197700276 BRANCH=none TEST=emerge-brya coreboot Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I14907faeb631193715b1e0e451e427fb79a68279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/taeko: Add initial fw config for taekoJoey Peng
According to config.star fw mask definition, add initial FW_CONFIG id. BUG=b:194649740 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Cq-Depend: chrome-internal:4072654 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ifef750338d777b76e9710d6bca9a166120db6a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08mb/google/brya/var/redrix: Enable SaGv supportWisley Chen
Enable SaGv support for redrix BUG=b:198536984 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I54402dfde5db4106a4e0d891c19592fda39a1099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-07mb/google/brya/variants/gimble: update fw_config.c for next build phaseMark Hsieh
Update fw_config.c based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:190688567 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-04 11:07:11 +0000