diff options
| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2021-09-15 13:39:21 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-28 20:08:23 +0000 |
| commit | 836a7f92d279897d1b286590d11c95ebf316ef14 (patch) | |
| tree | 980c2f9a00f5a402dd9546a1aa07e6d0b76e5894 /src/mainboard/google/brya | |
| parent | 245a194efc189369e34a28b995296597183eda6c (diff) | |
mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that taeko can successfully
boot into OS with non-serial coreboot.
BUG=b:199969366 & b:200711149
TEST=Build FW and test with non-serial FW reboot 20 times pass.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko/gpio.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index a06659d25c..17004eea49 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -156,6 +156,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -166,15 +168,20 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), }; -const struct pad_config *__weak variant_gpio_override_table(size_t *num) +const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); return override_gpio_table; } -const struct pad_config *__weak variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; |