Age | Commit message (Collapse) | Author |
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This patch uses ACPI _PLD macros to add custom values for USB ports.
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C3 | | C0
C2 | | C1
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BUG=b:216490477
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
C2 C0 A3 A2
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C1 A1 A0
BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add fw_config probe for auido and enable BT offload support.
BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Based on latest schematic to update the gpio table.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Remove EEPROM power source interconnect with camera power on/off
and keep it always on.
There appears to be a rare case where the camera EEPROM is not
able to be read from. As a workaround, this patch leaves the
EEPROM power rail on in S0.
BUG=b:229049914
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The _DSM subfunction for the Nvidia GN20 supports 1 additional
subfunction, known as GPS, which is required to support GPU Boost. This
implementation is minimal, essentially letting the GPU manage its own
temperature.
BUG=b:214581372
TEST=abuild
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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During the GPU power down sequence, each power rail should reach below
at least 10% before the next rail is sequenced down; based on scope
shots for a board, conservative delays between each rail are added;
they will likely be more fine-tuned later on.
BUG=b:233959099
TEST=sequence verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add OVTI8856 information for craask
BUG=b:232656913
TEST=Build and boot on craask
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign Vendor
H58G56AK6BX069 2 (0010) Hynix
BUG=b:227595062
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.
BUG=b:214581372
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set different power limit values using host command to detect charger
type from ec.
Scenario:
1. With 90W customized adapter, set to baseline.
2. With 170W customized adapter, set to performance.
3. With above 90W barrel jack/type-c adapter, set to performance.
4. With below 90W barrel jack/type-c adapter, set to baseline.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Follow GPIO_Table_0527.xlsx to update gpio configuration.
- Set GPP_A15 to NC.
- Set GPP_A20 to TCP_DP1_HPD (native function1).
BUG=b:225384873
TEST=Build and boot to Chrome OS.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow thermal table from thermal team.
Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.
BUG=b:230829301
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nereid
BUG=b:233030505
BRANCH=None
TEST=Build FW and test on Nereid board.
Verified thermal throttling successfully when participant reaches temp
threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are
reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: I195f4b507ee57948751f0119735d8350dfce984b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
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This patch configures external V1p05/Vnn/VnnSx rails for Craask
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:233717182
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, enable ISH when UFS is
present.
For more context on why this is necessary, see CB:62662 which enabled
UFS and ISH for adlrvp_n.
BUG=b:234136500
TEST=Build test. Will test that UFS works once we have hardware.
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniil Lunev <dlunev@chromium.org>
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This commit adds the skolas baseboard, which is basically the brya
baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder
Lake SoC.
This commit also adds the skolas baseboard variant skolas4es.
Since this baseboard is identical to the brya baseboard with the
exception of the SoC used, the new baseboard and the new baseboard's
first variant will be a copy of the current brya baseboard and brya0
variant.
For now, the skolas baseboard and skolas4es variant will continue to
use ADL-P. This allows for two benefits:
1. software to be proven out on existing hardware prior to RPL SoC
support landing, and
2. allows us not to have to wait for RPL SoC changes prior to getting
the mainboard changes in place
Once the RPL SoC code has merged, I will update the skolas baseboard and
skolas4es variant to use RPL instead of ADL.
BUG=b:229134437
TEST=util/abuild/abuild -p none -t google/brya -x -a -c max
Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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All Osiris SKUs use the new RGB gaming keyboard,
so don't need the fw_config to decide keyboard matrix.
BUG=b:220800586
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19211c345de0b315d65ec64efc70826e81315810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Craask uses CNVi WLAN, so disable the PCIe-related GPIOs.
BUG=b:229040345
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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BUG=b:210970640
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Starting with id 2, boards switched the memory SMBus slave address, and
use 0x50, 0x52.
BUG=b:233975373
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I47b069377046652ba4d278733a15bbca98bdb739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 2500 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
K3LKLKL0EM-MGCN
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Select vbt bin files based on DB_DISPLAY field of FW_CONFIG.
BUG=b:233690293
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and
make it default for nissa.
BUG=b:202783191
TEST=build nissa and brya firmware, check they're still 32MB
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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To support speaker AMP CS35L53-CWZR'S I2C needs to split to two
I2C ports
BUG=b:207333035
BRANCH=none
TEST=built and verified speaker
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
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This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9.
Reason for revert: Enable i2c7 for amp changing to 2 channel
because vell setting amp on i2c0 and i2c7 on next phase
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kinox has four temperature sensors. Modify the target of DPTF active
policy to map correct temperature sensor.
BUG=b:231380286
TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec
comsole.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The dGPU used for some Brya projects requests 32 bits of address space
for one of its BARs via the Resizable BAR mechanism. This Kconfig is
currently set at 29 bits for brya, so the allocation currently is
capped at 29 bits. This patch sets the limit to 32 bits for brya
boards, which is enough for the GPU.
BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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While testing the power sequencing code for the GPU, a few mistakes were
found. This patch fixes those errors:
1) FBVDD load-switch enable is active-low
2) NVVDD VR enable is active-high
3) GPU_PERST_L should be driven low during GPIO table programming
4) The BAR saving code missed the top 32 bits of 64-bit BARs
5) sequence_rail() assumed the pwr_en_gpio and pg_gpio were the same
polarity
6) PEG vGPIOs were not programmed to the correct NF
BUG=b:233552225
TEST=dGPU is able to successfully enumerate over PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I85767d382012a0c7dfdb1f849768e0160f06c273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add fw_config support NMAX98360_ALC5682VS_I2S_2WAY and I2S2 vgpio
config and enabling cnvi_bt_audio_offload UPD bit.
BUG=none
TEST=emerge-brya coreboot
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I64a4e5479905911b2e9d1597b78131720abb689e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Correct the USB-C port setting according to schematics.
AP log:
port C0 DISC req: usage 1 usb3 3 usb2 1
port C1 DISC req: usage 1 usb3 1 usb2 3
BUG=b:233554817
BRANCH=brya
TEST=emerge-draco coreboot chromeos-bootimage
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Iea4aee19dff8e0bc863be46532f89e81f52f281b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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We need to put USB setting in mux order.
BUG=b:234103724
TEST=Type C mux configuration is correct.
Wrong:
added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
Correct:
added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f8dbee35159960d17107e23fcde825a38c7de4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
| MLB DB | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibd36fb961de9e9af9da1fd885eeb958c833d38bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A | MLB DB | A
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A | MLB DB | A
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Icd56c650a03c5db6e1e68e4ca4c9f0c068a7a430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | A0
C0 | MLB DB |
A | |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia493fd28c362d2c0c343c2d121f6611cfd8f7f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
| | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | C1
| MLB DB | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
A | | A
C0 | MLB DB | C2
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia1e95aba2f7d02131b0b0cdd6c7211a23e355084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | A0
C0 | MLB DB | C1
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I68fb940825bfcf7c77ca3015372025e47e7fcc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature as mentioned in doc #572349.
BUG=b:229804441
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The baseboard uses port USB2 #9, and USB3 #1, but vell does not,
therefore set the port configuration to EMPTY.
Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Correct empty tcss port to meet Moli's schematic design.
BUG=b:233834605
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Enable SaGv support for Banshee
BUG=b:233930777, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I22810f422e3f1d6dd1f64d93e6d7aff5593ff739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
Moli has USBA port4 but Brask didn't use the port4,
so enable USBA port4 in moli.
BUG=b:232656163
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
Add WiFi SAR table for mithrax.
BUG=b:231491014
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I847debd7c817225b5b1777c798a14ef10aee3471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:232892200
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I65e3fef581ee06fa049e831f246da1328a08518c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3dfc5862fdcc663d9e0adbfda30c940d43b49b4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id6ee977fbda3118229677aa76e5394f5592c3da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add support for MB level dll tuning.
This patch sets the eMMC dll tuning parameters to default values needed.
There was issue observed on some eMMC devices which failed to boot in
HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters
that needs to be set. We observed these values helped to fix the issue.
While we get the verified default values set from FSP directly, adding
it here to use it as the custom dll values needed.
BUG=b:230403441
TEST=Build and boot nivviks board. Verify the eMMC dll parameters are
overridden.
[INFO ] usha: After override dll_params
[INFO ] usha: emmc_tx_cmd_cntl=505
[INFO ] usha: emmc_tx_data_cntl1=909
[INFO ] usha: emmc_tx_data_cntl2=1c2a2828
[INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c
[INFO ] usha: emmc_rx_cmd_data_cntl2=10049
[INFO ] usha: emmc_rx_strobe_cntl=11515
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Set custom_pld of each USB port (both Type A and C) with actual
physical location values.
BUG=b:214025396
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ic84b9aae1501e36c2794382aabcf8225eef7783b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.
BUG=b:231400227
TEST=Build and suspend_stress_test -c 5 pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iae33068c4622f91d5cebb867e4b10f3834ce8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
add USBC0_RETIMER into 2, 3 bits for usb retimer.
BUG=b:232486478
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
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Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1
values.
1. Modify baseline PL1 min_power from 15000 to 12000.
2. Modify baseline PL1 max_power from 17000 to 25000.
BUG=b:231380286
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Nivviks
Add DPTF passive and critical policies for ADL-N Nivviks design.
Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1.
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board.
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Create the kuldax variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:233380254
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULDAX
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
1. Add wifi sar table for volmar
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:233319626
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
H9JCNNNBK3MLYR-N6E
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.
BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Enable SaGv support for crota
BUG=b:229600878
TEST=FW_NAME=crota emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch configures external V1p05/Vnn/VnnSx rails for Nivviks
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379
TEST=Verify the build for primus board
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.
BUG=b:214581763
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The agah variant will include an Nvidia GN20 series GPU, therefore
select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective
ASL code into the DSDT.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The audio codec used by crota has a level-sensitive interrupt,
therefore configure the GPIO pad as level-sensitive.
BUG=b:230418589
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 5 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently, the LTE pins are enabled in gpio.c, then disabled in
fw_config.c if LTE is not present. However, since there's a short delay
between mainboard_init() and fw_config_handle(), this means that when
LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR
sensor) will be floating for a short period of time.
Rework the GPIO config so that the LTE pins are disabled in the
baseboard, then enabled in fw_config.c for variants using LTE. However,
this doesn't work for WWAN_EN and WWAN_RST_L since they need to be
enabled in bootblock. So these are instead enabled in the variant
gpio.c, then disabled in fw_config.c if LTE is not present.
BUG=None
TEST=LTE still works on nivviks
Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:231291431
TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only
is not handled by EC, so we need to set dual route to wake the system.
BUG=b:229142661
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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1. Update override devicetree based on schematics.
2. Update Kconfig based on schematics.
BUG=b:229191897
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add the support RAM parts for mithrax.
Here is the ram part number list:
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
K4UBE3D4AA-MGCR 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:A 2 (0010)
MT53E1G32D2NP-046 WT:B 1 (0001)
BUG=b:229191897
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Configure GPIOs according to schematics
BUG=b:229191897
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus
addresses to 0x52, 0x50.
BUG=b:231398371
TEST=Build and boot to OS with either 1 or 2 DIMM slots populated.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:227801913
TEST=build and boot nivviks
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is just physically remove option board from motherboard,
so it just need one vbt, and it don't need the fw_config to decide
which vbt will be return.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is physically remove option board from motherboard,
so set default vbt has option-DP setting and only return it.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs.
BUG=b:218929856
TEST=Boot to OS on nivviks and check that WLAN still works.
Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are
only supported on nirwen, an additional nissa variant based on nivviks
and sharing the nivviks coreboot target.
BUG=b:218929856
TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS
will be tested once nirwen boards are available.
Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nirwen is an additional nissa reference board which is almost identical
to nivviks, so is reusing the nivviks coreboot variant. However, there
are two GPIO changes, so update the GPIO tables to handle these based on
board_id.
nivviks:
GPP_D6 -> WWAN_EN
GPP_E13 -> NC
nirwen:
GPP_D6 -> SSD_CLKREQ_ODL
GPP_E13 -> WWAN_EN
BUG=b:218929856
TEST=Boot to OS on nivviks
Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen
garage is enabled/disabled as expected.
Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC
is enabled/disabled as expected.
Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch sets the RComp resistor values to default values needed.
BUG=b:231202733
TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set
to default values from debug FSP log.
[SPEW ] Updating Rcomp Targets:
[SPEW ] RcompTarget[RdOdt]: 48
[SPEW ] RcompTarget[WrDS]: 30
[SPEW ] RcompTarget[WrDSCmd]: 20
[SPEW ] RcompTarget[WrDSCtl]: 20
[SPEW ] RcompTarget[WrDSClk]: 20
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2c7a54c49e282446ece77ca406951782282a009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota.
BUG=b:231686917
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C
BUG=b:231684121
TEST=local build and tested with ELAN touch screen
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ide005a0681e236c3102090c1c36ab81926849000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD
card is enabled/disabled as expected.
Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Ti50 firmware versions below 0.0.15 don't support the firmware_version
register and trying to access it causes I2C errors. Some nissa boards
are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading
the firmware version and select it for nissa. The firmware version is
only read to print it to the console, so it's fine to skip this. This
workaround will be removed once all ODM stocks are updated to 0.0.15 or
higher.
A similar workaround Kconfig was added in CB:63011 then removed in
CB:63158 which added support for separate handling of Cr50 and Ti50.
But we actually still need this workaround until all Ti50 stocks are
upgraded to 0.0.15 or higher.
BUG=b:224650720
TEST=Boot to OS on nereid with Ti50 0.0.14
Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need
to set it as INT in coreboot to make the IRQ work.
BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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