diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2022-05-25 16:36:57 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:45:04 +0000 |
| commit | 4757053e8323d72cc5ee7605dcbcfe1e9577bceb (patch) | |
| tree | 5f6048ee9abc4ce2e03ed6b88b216f05eb7ecc5b /src/mainboard/google/brya | |
| parent | 4baadff264c35f069665d13d830d8684fae6ebe2 (diff) | |
mb/google/brya/var/nissa: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature as mentioned in doc #572349.
BUG=b:229804441
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 83cd62fad8..8722d718d8 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -25,6 +25,8 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Enable CNVi BT register "cnvi_bt_core" = "true" |