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This signal gets deasserted by the WWAN modem to reactivate the PCIe
link when in low power mode. In order to handle this efficiently, the
kernel needs to set up an interrupt.
BUG=b:301150499
TEST=Compiled and tested on google/redrix
Signed-off-by: Paweł Anikiel <panikiel@google.com>
Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Vendor DRAM Part Name Type
MICRON MT62F512M32D2DR-031 WT:B LPD5
HYNIX H9JCNNNBK3MLYR-N6E LPD5
HYNIX H9JCNNNCP3MLYR-N6E LPD5
MICRON MT62F1G32D4DR-031 WT:B LPD5
HYNIX H9JCNNNFA5MLYR-N6E LPD5
MICRON MT62F2G32D8DR-031 WT:B LPD5
SAMSUNG K3KL6L60GM-MGCT LPD5x
MICRON MT62F1G32D2DS-026 WT:B LPD5x
SAMSUNG K3KL8L80CM-MGCT LPD5x
HYNIX H58G56BK7BX068 LPD5x
MICRON MT62F2G32D4DS-026 WT:B LPD5x
SAMSUNG K3KL9L90CM-MGCT LPD5x
HYNIX H58G66BK7BX067 LPD5x
BUG=b:304920262
TEST=Run part_id_gen tool without any errors
Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update overridetree to correct FP_MCU fw_config settings.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update overridetree for TouchPad.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the following register value to make SX9324 work normally
"ph0_pin" = "{1, 3, 3}"
"ph1_pin" = "{3, 2, 1}"
"ph2_pin" = "{3, 3, 1}"
"ph3_pin" = "{1, 3, 3}"
"ph01_resolution" = "512"
"ph23_resolution" = "1024"
"startup_sensor" = "1"
"ph01_proxraw_strength" = "2"
"ph23_proxraw_strength" = "2"
"avg_pos_strength" = "256"
"cs_idle_sleep" = ""gnd""
"int_comp_resistor" = ""lowest""
"input_precharge_resistor_ohms" = "4000"
"input_analog_gain" = "3"
BUG=b:295109511
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Enable EC keyboard backlight for dochi.
BUG=b:299284564
TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage
Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Use runtime detection for touchscreens.
BUG=b:289962599
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia43ada8b3b6dbee95dbadacc353106e0f8f37549
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Based on schematics and confirm with EE to remove TOF function.
BUG=b:290891557
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPIOs according to schematics revision 20231013.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I1ccab46b9f622fb98920d316c31800f39dc8ff95
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78384
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Create the anraggar variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:304920262
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANRAGGAR
Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Disable SD card GPIO with fw_config for quandiso units without SD
card and pull GPP_H12 to high to match the spec.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
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Update overridetree base on schematics revision 20230923.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support an RPL SKU on dochi, it must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL
FSP headers.
BUG=b:299570339
TEST=emerge-brya intel-rplfsp coreboot
coreboot-private-files-baseboard-brya
Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Pull GPP_C1 to high in ramstage to meet touchscreen power sequence.
BUG=b:302236370
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
& test touchscreen function on quandiso DUT
Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Configure GPIOs according to schematics revision 20230923.
TEST=emerge-brya coreboot
Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:303533832
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I575da55b96bf4deacec5c0992eae9930eb0745d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Measured the I2C frequency meets spec
- I2C0 (TPM): 949.7 Khz
- I2C1 (TouchScreen): 395.8 Khz
- I2C3 (Audio): 387.4 Khz
- I2C5 (Touchpad): 384.8 Khz
BUG=b:303356736
TEST=USE="project_joxer emerge-nissa coreboot"
and check all I2C devices measurement result
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I17dd1cb7800d00669f86fc6e2b350757695da881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78218
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Quandiso reserve bit 11 for mipi camera usage.
BUG=b:300574047
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:300573763
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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When service center repair touchscreen or touchpad will change
compatible device not specific one, the fw_config probe mechanism is not
convenient for service center. Removing touchscreen and touchpad
fw_config probe for the purpose.
BUG=b:297840605
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77538
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn off GPP_H13 (EN_PP3300_SD_X) in s0ix for power saving. It reduces
about 3mW of power consumption in s0ix on pirrha proto board.
BUG=b:300845527
TEST=Built and verified GPP_H13 voltage was 0V in s0ix.
Also verified SD card worked after s0ix for 20 times.
Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add VCM power control to configure 2.8V and reset pin, and VCM can
be powered on/off properly.
BUG=b:292907385
TEST=Run ITS test
Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0
Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add probe fw_config to USB C1/A0 port on daught_board for DB_1A sku.
BUG=b:294456574
TEST=emerge-nissa coreboot
Change-Id: I2261b0e4d2b673b6186a435cce8dc6a4ccacb0a7
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I1439f785cb9ceeefab9d24caa88e35bd43f68315
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Implement support for elan i2c touchscreen and use fw_config
to pick between i2c or HID-over-i2c touchscreen.
Support G2 TS have different slave address by fw_config
BUG=b:295272539
BRANCH=firmware-nissa-15217.B
TEST=build and verified touchscreen work
Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Convert TPM functions to return TPM error codes(referred to as
tpm_result_t) values to match the TCG standard.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert hex print values to use the %#x qualifier to print 0x{value}.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify the settings:
1)Add fw_config probe on USB type C for "DB_1C_LTE".
2)Add fw_config probe on USB type A for "DB_1A_HDMI".
BUG=b:296791122
TEST=build and check USB functions on craask
Change-Id: I2775098ab380995e62f264bc51a430762c256c4b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rather than disabling C State demotions for every single Raptor
Lake board due to an issue with S0ix, regardless of if they even
use S0ix, configure it in the mainboard.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:298337185
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=dochi emerge-brya coreboot
Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Add 4th sensor device for DTT tuning.
BUG=b:292134655
TEST=Built and verified DTT tool could monitor the new sensor device
Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
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Facilitates correct profile selection by SOF Windows drivers.
Profiles for nokris and quandiso will be added once correct board
configs can be determined.
TEST=build/boot Win11 on google/craask, verify correct audio profiles
loaded, audio functional.
Change-Id: Id4582b5dd74a4905ea509813ec99663577360095
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
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Add Makefile.inc to include five generic LPDDR5 SPDs for the following
parts for Dochi:
DRAM Part Name ID to assign
MT62F1G32D2DS-023 WT:B 0 (0000)
K3KL8L80CM-MGCT 1 (0001)
H58G56BK8BX068 0 (0000)
BUG=b:298337185
TEST=USE="project_dochi emerge-brya coreboot"
Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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1. Support world facing usb camera on usb2_port7.
2. Update MB/DB fw_config to distinguish LTE and non-LTE devices.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- GPIO changes:
GPP_B5 ==> I2C_P_SENSOR_SDA
GPP_B6 ==> I2C_P_SENSOR_SCL
GPP_H19 ==> P_SENSOR_INT_L
- I2C SX9324 support
- Disable GPIOs when sub board LTE not used
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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GPIO changes
- GPP_D8 ==> SD_CLKREQ_ODL
- GPP_D17 ==> SD_WAKE_N
- GPP_H12 ==> SD_PERST_L
- GPP_H13 ==> EN_PP3300_SD_X
Genesys Logic GL9750 support
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Quandiso doesn't support mipi WCAM.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update files copied from yavilla
- fw_config setting
- GPIO setting
- Kconfig setting
- overridetree setting
- SPD memory parts
- variant setting
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
flash bin file in DUT
Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brya queries the TPM in early ramstage (pre-device init) to determine
if the CR50 has support for long-pulse interrupts. If the TPM (and
underlying I2C controller) hasn't already been setup in verstage, it
will fail to do so in ramstage since the I2C controller has not yet
been initialized. To work around this, initialize the TPM in bootblock
for the non-vboot case, to ensure the I2C controller is set up when
needed in early ramstage.
TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem
console when initializing TPM in early ramstage.
Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make naming convention consistent across all functions return values.
BUG=b:296439237
TEST=Boot to OS on Skyrim
BRANCH=None
Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Boot to OS, check camera LEDs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn
for HDMI.
BUG=b:296791122
TEST=build and check HDMI function works on craaskana
Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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1. WIFI_SAR_ID_4: AX211
2. WIFI_SAR_ID_5: AX203 (without WiFi-6E)
BUG=b:293360900
TEST=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6c4705d25d927aaefbc8814ea1df3b4c36b30968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77790
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kuldax-refresh use USB Hub, add fw_config probe for USB Hub.
BUG=b:275335023
BRANCH=brya
TEST=Built and check firmware log.
Change-Id: Ib983ca527a891718f317336597faad66d076247f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Create the dochi variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:299570339
BRANCH=firmware-brya-14505.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DOCHI
Change-Id: Iadeb97bd217278cdf777ae350100313b4345ecf3
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77756
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add audio codec ALC5650 related settings.
BUG=b:289969623
TEST=emerge-nissa coreboot
confirm the device in kernel log.
Change-Id: I4b8a19e6248bd91cfc31feb84c6108413cd719e2
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77701
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG.
BUG=b:299852789
TEST=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Use fw_config for a dedicated pujjo1e intel wifi sar table.
BUG=b:293360900
Test=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent
confusion.
Origin: 0 --> SD_GL9750S
Modify: 0 --> SD_PRESENT
BUG=b:296505165
TEST=emerge-nissa coreboot
Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Without part no. in CBI, mainboard_get_dram_part_num returns null.
To prevent passing this null pointer to strcmp and avoid unexpected
behavior, proper handling is necessary.
BUG=none
TEST=emerge-brya coreboot
Change-Id: I47e42376c6b1347c56afaec218aed63c5469f0aa
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77646
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add data.vbt file for yavilla recovery image. Select INTEL_GMA_HAVE_VBT
for yavilla which currently have a VBT file.
BUG=b:298320552
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I72f98181b3487f8ae9acf6e0f2382a0204f7989c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Yaviks already disabled external V1P05, so disable V1P05 control pin
which controls the VCC_V1P105_EXT_1P05.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
SAR_ID_0 : Yaviks_Gfp2
SAR_ID_1 : Yaviks & Yavilla_MT7921
SAR_ID_2 : Yahiko_Gfp2
SAR_ID_3 : Yavilla_MT7922
BUG=b:298138654
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77559
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Configure the AUX pins as NC based on the FW_CONFIG setting when
the C1 port is not present.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Restore TPERST_HIGH to 160ms since it has beed validated in other
OEM projects and haven't heard any issue so far.
This change back commit d710c6d5a773 ("mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequence").
BUG=b:295277868
TEST=emerge coreboot
boot to system and check wifi connection is fine
Change-Id: Ifc66e596fc7b6efdc0c286ee187969c8774bdc80
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Currently pirrha's digitizer pen uses GPP_F12 for I2C HID interrupt
signal. But its IRQ number is the same as GPD2, which is used as
EC_SYNC_IRQ.
It caused EC driver loading error from dmesg:
cros_ec_lpcs GOOG0004:00: Failed to request IRQ 98: -16
cros_ec_lpcs GOOG0004:00: couldn't register ec_dev (-16)
cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
So change the digitizer pen interrupt type to GpioInt to prevent
the conflict.
BUG=b:292134655
TEST=Verified EC driver reported no error and pen device worked
Change-Id: Ieb88e87fcfb06544a4b5b5133b752aa821fab76a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77346
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on schematics and gpio table of pirrha, generate overridetree.cb
to configure internal devices and generate fw_config.c to override
GPIO configurations following FW_CONFIG.
BUG=b:292134655
TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage
Change-Id: I91013b0ad89e26f0a4c433c305c6b883d000f042
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77116
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Support Weida WDT8790A touchscreen.
BUG=b:297453122
BRANCH=firmware-brya-14505.B
TEST=touchscreen is workable and evtest shows WDHT2601
$evtest
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event10: sof-cs42l42 HDMI/DP,pcm=2
/dev/input/event11: sof-cs42l42 HDMI/DP,pcm=3
/dev/input/event12: sof-cs42l42 HDMI/DP,pcm=4
/dev/input/event13: sof-cs42l42 HDMI/DP,pcm=5
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: Elan Touchpad
/dev/input/event5: WDHT2601:00 2575:0921
/dev/input/event6: WDHT2601:00 2575:0921 Stylus
/dev/input/event7: WDHT2601:00 2575:0921 Stylus
/dev/input/event8: DELL Dell USB Entry Keyboard
/dev/input/event9: sof-cs42l42 Headset Jack
Change-Id: If9539afaf891c8352bc7fc8e548fd77ea57ea6ca
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77575
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add intel wifi sar table for yahiko
BUG=b:298280621
BRANCH=firmware-nissa-15217.B
TEST=build, enable iwlwifi debug option, and check dmesg
Change-Id: I38d2e640fc2f7cbde3986474ca1bf7de9b2d25b4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77585
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add variant of NAU8318(SPK) + NAU88L25B(Headphone) audio support
on brya and skolas board.
In fw_config settings, reuse max98360_enable_pads[] due to
identical i2s configurations as nau8318.
In addition, separated GPP_R7 as SPK_BEEP_EN pin.
BUG=b:236561637
TEST=emerge-brya coreboot
BRANCH=none
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Suggested-by: David Lin <CTLIN0@nuvoton.com>
Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This change causes a freeze during boot on an RPL-UR that does not have
the memory part string in the CBI.
BUG=b:296353047
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot
problematic DUT to kernel.
This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365.
Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE
Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set customized_leds value for RTL8111K to fix led can't work.
BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.
Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS
Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.
BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko.
BUG=b:294928078, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Icb952c0716d446d5feb5580f357120a27193284e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the quandiso variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_QUANDISO
Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Separate constitution and intrepid wifi sar table in variant.c
BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.
Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I551d71d968abb6a9cadbc0f87bc9258768db1fca
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77275
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7ed982c9dcf755c97f26cc43b3dc05b898e4150a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77274
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt files for all variants supported by current brya, brask,
and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants
which currently have a VBT file.
TEST=build/boot various brya variants (banshee, osiris, redrix)
Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.
Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.
BUG=b:284799726
TEST=Able to see the early splash screen on google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2449bf97d6c82cb08f603b29643cc261738b5379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Disable pins for SD card based on fw_config.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I0b383d1b00056a69ba925bb5203dc4ca026b9d8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77105
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support MIPI driver and DA7219 driver for pirrha.
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I6a8f0f942a54909627aad3bf447dc7225f57cef2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Correct TPM I2C BUS number for pirrha
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I9fa0b46db752d02368f19ce8c58a4122b371c100
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77164
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file.
It includes MIPI power sequence data for panel.
BUG=b:295112773
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:292134655
BRANCH=nissa
TEST=Boot to OS on pirrha ADV board
Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Implement support for elan i2c touchscreen and use fw_config
to pick between i2c or HID-over-i2c touchscreen.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified touchscreen work
Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With this change TPERST_HIGH could met spec.
Before
160ms
After
460ms(met spec min=400ms)
BUG=b:295277868
TEST=emerge coreboot
EE measured power sequence met spec
boot to system and check wifi connection is fine
Change-Id: Ifb909a55b36f2366132c3e20021c4bde4bc87a05
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add GPIO table for pirrha based on pirrha ADV board schematics.
BUG=b:292134655
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76882
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I7a775838358e7abe3f03d0ae65fb619c15dbad6f
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76875
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update eMMC DLL settings to solve eMMC boot error.
BUG=b:294196963
TEST=Reboot test 1000 times pass
Change-Id: I16f3aa6aab4c58369770acad92c7ee5518c719ab
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77082
Reviewed-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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NVM has 8KB to store camera module related settings and
parameters. According to NVM hardware spec, the NVM size should be
0x400 and the width size should be 0x08.
Re-set the right NVM format and ensure camera related configs can
get the correct module information.
BUG=b:294155898
TEST=none
Change-Id: I58932bc0f3dd935aa0ea8e68b2a4b0ae4907b316
Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76893
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
TEST=build/boot Windows/linux on redrix?, verify touchscreen functional
in OS, dump ACPI and verify only i2c devices actually present on the
board have entries in the SSDT.
Change-Id: I0273014b2d164f67f503da7b968a09256bffb43c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74929
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For brya variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard). This will allow coreboot
to detect the presence of i2c touchscreens during ACPI SSDT generation
(implemented in a subsequent commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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