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2022-05-16mb/google/brya: Remove Rcomp resistors override for NissaUsha P
This patch sets the RComp resistor values to default values needed. BUG=b:231202733 TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set to default values from debug FSP log. [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 48 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 20 [SPEW ] RcompTarget[WrDSCtl]: 20 [SPEW ] RcompTarget[WrDSClk]: 20 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2c7a54c49e282446ece77ca406951782282a009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750Terry Chen
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota. BUG=b:231686917 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/crota: Change ELAN touchscreen i2c address and HIDTerry Chen
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C BUG=b:231684121 TEST=local build and tested with ELAN touch screen Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Disable SD card based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD card is enabled/disabled as expected. Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman
Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIOEric Lai
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-13mb/google/brya/variants/osiris: Init devicetree for osirisDavid Wu
Init basic override devicetree based on schematics BUG=b:224423318 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13mb/google/brya/variants/osiris: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for osiris BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-05-12mb/google/brask/variants/moli: Set GPP_E14 as the default value.Raihow Shi
We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14 as the default value to let HDMI-DDIA get hot plug detection. BUG=b:231769129 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/nissa/var/craask: Add supported touchpadTyler Wang
Add related settings for synaptics touchpad. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-12mb/google/brya/var/agah: Enable PCIe RP 3 for LANTony Huang
Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11mb/google/brya/var/crota: enable wifi sarScott Chao
BUG=b:216594621 BRANCH=brya TEST=build pass and SAR table be changed according to tablet/ desktop mode Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11mb/google/brya/var/kinox: Disable thunderbolt interfaceDtrain Hsu
Disable all of the TBT devices in devicetree since kinox doesn't support thunderbolt. The change also need to disable TBT in fitimage (chrome-internal:4731094). BUG=b:231654363 TEST=Build and run on DUT. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11mb/google/brask/variants/moli: correct tcss_usb3 portCasper Chang
Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brask/variants/moli: enable BT offloadCasper Chang
Enable BT offload of NAU88L25B on Moli with fw_config NAU88L25B_I2S. BUG=b:220814038 TEST=emerge-brask coreboot, Check BT offload enabled in CPU log and audio works. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I72d91d2dafffa7d9604b7dd3d697cb3b2b04b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brya/var/crota: Fix codec reset pin in overridetreeTerry Chen
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brask/variants/moli: disable ASPM on pcie_rp 6Raihow Shi
Currently coreboot will hang on ASPM on pcie_rp 6, so disable ASPM to let it go into kernel. BUG=b:231400217 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I79a80d97d168f40e58774e5652967d659daa323c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-06mb/google/brya/variants/crota: Enable Bluetooth offload supportTerry Chen
Enable CnviBtAudioOffload UPD from Intel Guideline BUG=b:230418589 TEST=emerge-byra coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05mb/google/brya/var/vell: Remove unused i2c7 settingsGaggery Tsai
This patch removes unused i2c7 settings. Accroding to EVT schematic, i2c7 is reserved for AMP but resistors are unstuffing. BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05mb/google/brya/var/agah: Add GPU power sequencingTim Wawrzynczak
This patch adds support for power sequencing of the Nvidia GN3050 for agah, which uses PCH GPIOs to control the 5 power rails required for the GPU. The GPU is power sequenced on during mainboard initialization, then it is enumerated on the PCI bus and its resources are assigned. This GPU will be used in a sort of "hybrid graphics" mode, therefore during finalization, since its PCI BARs are saved into ACPI memory and the GPU is not required upon initial boot, the GPU is power sequenced off. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-05mb/google/brya/var/crota: setting for codec reset pinTerry Chen
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-04mb/google/brya/var/taeko{4es}: Remove extraneous __weak attributesTim Wawrzynczak
Functions that are intended to override weak ones defined in the baseboard should not also be declared weak, otherwise how would the linker know which copy to keep. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-04mb/google/brya/var/crota: Enable webcam powerTerry Chen
Based on the schematic bernadino 14 adl-p 20220318.pdf to set GPP_D16 to enable webcam power BUG=b:230289857 BRANCH=none TEST=build and notice log kernel v5.10 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I01c73006d24b00be348655334232bea5eeb312e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-04mb/google/brya: Add EC mux device to brya0Prashant Malani
Add entries to the devicetree override for brya0 and enable the Kconfig to ensure the Chrome OS EC Mux driver is build tested. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532 Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-02mb/google/brya/var/kinox: Update power control settings for 15W SOCDtrain Hsu
Kinox keeps 65W barrel jack for Intel Pentium/Celeron SOC. Considering the dynamic loading of 65W adapter, it can up to 130% with 20ms. Update power settings to below for preventing blowing out the adapter. - Psys_Pmax 135W - PL2 39W - PL4 72.5W - Psys_PL2 65W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv For Intel Core processor, Kinox will use 90W barrel jack. Modify default power settings as below. - Psys_Pmax 135W - PL2 55W - PL4 123W - Psys_PL2 90W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hou-hsun Lee <hou-hsun.lee@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-02mb/google/brya/var/osiris: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for osiris. BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I501155531bff8c59641e88ea61aab623cb9a1868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-04-29mb/google/brya/var/agah: Change Aux settings to TCSS port 2Tony Huang
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2. Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I2d26777e850187aee0b676de13dff915474fed7b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/brya/var/crota: fix Goodix touchpadTerry Chen
- Fix Goodix hid and hid offset BUG=b:230415144 BRANCH=brya TEST=build and boot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I5a5c1cdca0cec15d65fe62a3104652d2d347fd54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/brya: disable early EC sync for nereidPeter Marheine
The ITE EC used on Nereid can take a long time to update, and especially too long to erase. There is a 1 second timeout enforced on the EC erase command, but Nereid's IT81302 will typically take about 5 seconds to complete erase, and could take as long as 30. Since this affects any Nissa variant using an ITE EC and it's nice to make the entire Nissa project consistent, this change disables early sync for all Nissa boards. BUG=b:222987250 TEST=EC software sync is no longer attempted (and thus does not fail) on Nereid. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2022-04-27mb/google/brya/var/banshee: Update the FIVR configurationsFrank Wu
This patch enables V1p05 and Vnn external bypass VRs for Banshee. BUG=b:207116793 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Idb56890db40f90f163d8dadf5bf7c7335469771a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63860 Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/brya/var/vell: Enable TBT PCIe root port 3Gaggery Tsai
This patch enables TBT PCIe root port 3. BUG=b:230464233 TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and ensure 07.3 is in the list. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/nissa/var/craask Add device settingsTyler Wang
Add the configuration in device tree: 1. Add speaker codec and speaker amp settings 2. Add Elan touchscreen settings 3. Add WFC and usb settings 4 Add Elan Touchpad settings 5. Add WiFi configuration 6. Add LTE settings BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iabf7f864082714ef1fecdee984fbebf1f3f0a672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Add GPIO tableTyler Wang
Fill GPIO table for Craask. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT62F1G32D4DR-031 WT:B MT62F512M32D2DR-031 WT:B BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/adl/chip.h: Rename max_dram_speed to include unitsScott Chao
The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-27mb/google/brya/var/crota: update gpio configurationScott Chao
- enable CPU PCIe VGPIO for PEG60 - enable GPP_C3/ GPP_C4 native function - set unused GPIO to NC BUG=b:229584785 BRANCH=none TEST=build and boot into kernel v5.10 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: enable boot from SSD/ eMMCScott Chao
- Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and boot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: Limit dram speed to 4800 MT/sScott Chao
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1) page 121 recommends a maximum DRAM speed of 4800 MT/s. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/crota: modify DQ/ DQS tableScott Chao
BUG=b:229547171 BRANCH=none TEST=pass memory training with error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If6acf8cb9474f816374743fd1e800da46958993d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/vell: Fix camera LED flicker problemShon Wang
Camera LED flicker 3 times or so as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot preventing camera LED flicker. Corrects that by explicitly sequencing the reset GPIO and power GPIO BUG=b:219644184 TEST=Build and boot on vell, observe whether camera LED flickers Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-24mb/google/brya: Create mithrax variantJohn Su
Create the mithrax variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:223091246 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MITHRAX Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-24tpm: Allow separate handling of Google Ti50 TPMJes Klinke
A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-22mb/google/brya/var/taniks: Configure Acoustic noise mitigationleo.chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:227165770 TEST=build FW and system power on. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22mb/google/brya/var/taniks: Add WiFi SAR table for taniksleo.chou
Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/brask/variants/moli: update overridetreeRaihow Shi
Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-04-21mb/google/brya/var/taeko: Add WIFI SAR support for tarloJoey Peng
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:226684990 TEST=emerge-brya coreboot Cq-Depend: chrome-internal:4676926, chrome-internal:4686953 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9852553f5c91494db845d45a94e2566248538bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/brya/var/osiris: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brya: Create osiris variantDavid Wu
Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%Robert Chen
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/brya/var/brya0: configure gpio for headsetAmanda Huang
Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function enable with ALC5682I+MAX98360. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-04-20mb/google/brya/var/brya0: Swap TPM and touchscreen I2C busAmanda Huang
Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/google/brya/var/redrix: Add alias back to RP6 WWAN deviceTim Wawrzynczak
This alias name is required for the mainboard.c code to generate the appropriate power-off seqeuence for use during orderly S5 shutdown from the OS. It had been accidentally removed, but is required, so this patch adds it. BUG=b:227788351 TEST=compile Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20mb/google/brya/var/anahera{4es}: Enable power saving for Smart CardWisley Chen
Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya: Disable PCH USB2 phy power gating for felwinterSridhar Siricilla
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brask/variants/moli: update type-c setting in overridetreeRaihow Shi
Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/brask/variants/moli: add delay time to rtd3-coldRaihow Shi
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brask/variants/moli: remove i2c1 in overridetreeRaihow Shi
Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brask: fix boot beepDtrain Hsu
Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK. BUG=b:229345416 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot and verify if the buzzer beeps. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brask/variants/moli: Pick VBT based on FW_CONFIGRaihow Shi
Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG. BUG=b:220241277 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750Wisley Chen
select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s. BUG=b:229213455 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/nissa: Add gpio lock pinsEric Lai
Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brya: Add Kconfig for TPM I2C busRaihow Shi
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driverTerry Chen
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/google/brya/var/kano: Configure Acoustic noise mitigationDavid Wu
Setup the following acoustic noise mitigation features: 1) Slew rate for both IA and GT domains to 1/8 2) Disable Fast package C ramp BUG=b:229046516 TEST=build and verified by power team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifb5700391e33818878994f205acae7ee3b1b96d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/google/brya: Add variant_init and variant_finalize callbacksTim Wawrzynczak
Some brya variants may need to initialize and finalize some variant-specific devices during ramstage, therefore add the commonly-used hooks and callbacks to support this. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-13mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcntReka Norman
Configure lcnt and hcnt directly to give the required frequency, tHIGH and tLOW, instead of using rise and fall times. Aim for a frequency of 390 kHz to make sure it doesn't exceed 400 kHz on different boards. BUG=b:227517802 TEST=Probe the clock line and check that it meets the requirements for frequency, tHIGH and tLOW. Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya: Create craask variantTyler Wang
Create the craask variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASK Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-13mb/google/brya: Add missing parameter name to variant_generate_s0ix_hookReka Norman
Fixes the following build error: src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook': src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted void __weak variant_generate_s0ix_hook(enum s0ix_entry) ^~~~~~~~~~~~~~~ BUG=None TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya/var/nereid: Enable OZ711LV2LN SD card controllerReka Norman
Select the Bayhub LV2 driver, and implement power sequencing as per the datasheet. BUG=b:223304542 TEST=Check that connecting an SD card works as expected in the OS. Probe the EN and RST signals and check the timing requirements are met. Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-13mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1Amanda Huang
Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-12mb/google/brya/var/vell: add WWAN power sequence setting for vellRobert Chen
Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/brya/var/taniks: Enable Genesys L1 max entry delayJoey Peng
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/brya/var/nereid: Add WLAN power sequenceReka Norman
There are currently two issues related to the WLAN power sequencing on nereid: - If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck in S3. - During warm reboot, if we only assert RST without pulling the power low, then the kernel crashes. As a workaround while we investigate these issues, we pull the EN high in S5, then actively drive it low in bootblock and high in romstage to make sure it goes low during warm reboot. BUG=b:227694137, b:225261075 TEST=Cold boot succeeds, and there's no kernel crash during warm reboot. Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07mb/google/brya/var/nereid: Enable pen garageReka Norman
BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman
Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06mb/google/brya: Enable dynamic debug capability for brya familySridhar Siricilla
The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-04mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHzEddy Lu
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/google/brya/var/nereid: Add separate VBT for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Cq-Depend: chrome-internal:4650256 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ixAlan Huang
Turn off the NFC power which is controlled by GPP_D3 to save power in S0ix states. For an USB device, the S0ix hook is needed for the on/off operations to take place. BUG=b:202737385 BRANCH=firmware-brya-14505.B TEST=measure the voltage of GPP_D3 in S0ix states Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200msCasper Chang
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:223936777 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1Reka Norman
C0 has no redriver, so enable SBU muxing in the SoC. C1 has a redriver which does SBU muxing, so disable SBU muxing in the SoC. However, this also disables AUX biasing when the pins are configured as NF6. So instead configure the C1 AUX bias pins as GPO. BUG=b:227259673 TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-03-31mb/google/brya/var/agah: Replace amp max98390 with max98360Tony Huang
Based on the latest schematic, agah will replace the Maxim 98390 speaker amps with Maxim max98360. This patch updates the devicetree entries to reflect that. BUG=b:210970640 BRANCH=brya TEST=emerge-draco coreboot Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31mb/google/brya/var/agah: Add GL9750 SD card reader supportTony Huang
BUG=b:210970640 TEST=emerge-draco coreboot Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31mb/google/brya/var/kinox: set GPP_D0 to NCDtrain Hsu
Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support fingerprint. This patch sets GPP_D0 to NC for matching schematic. BUG=b:214025396 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-30mb/google/brya/var/kano: Remove SAR sensorDavid Wu
RF team comfirmed that SAR sensor is not necessary for MP, therefore remove the corresponding entries from the devicetree. BUG=b:202978964 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I31faf18563848f8d6787fe70bfb28006efea8427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/variants/crota: Add memory config for crotaTerry Chen
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30Revert "mb/google/brya/var/kano: adjust I2C3 speed"David Wu
This reverts commit 65aaccda5910e9c74aaa2a44ea84119d9476c902. Reason: 1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000 2. Measure DVT I2C3 speed < 400KHz. BUG=b:215095284 TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/variants/crota: init overridetree for crotaTerry Chen
init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf BUG=b:226315394 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RXFrank Wu
Update the GPP_D12 according to USB_C3_LSX_RX. BUG=b:225081954 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The device can be recognized when it is attached in port3. localhost /sys/bus/thunderbolt/devices # ls 0-0 1-0 1-0:3.1 1-3 domain0 domain1 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarloJoey Peng
Add thermal table settings for tarlo which shares the same firmware with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/nissa/var/nivviks: Move WWAN power on sequence forwardEric Lai
Move WWAN power on sequence from OS to coreboot. This can save the WWAN initial time about 10S. Another purpose is power resource be removed because we don't power off the LTE in S0ix. BUG=b:223490884 TEST=FM101-GL work as expected. Enumerate time from [ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module [ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 17.760224] usb 4-2: SerialNumber: 9c88998f to [ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module [ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 4.019762] usb 4-2: SerialNumber: 9c88998f Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-30mb/google/brask/variants/moli: update GPIOs for moliRaihow Shi
Follow the Moli GPIO Table_20220324.xlsx to update it. 1.Set A15 as the default value. 2.Set A14, A19 NC. 3.Set C3, C4 as the default value. 4.Set D9 as the default value. 5.Set E5, E13 as the default value. 6.Set R4, R5 as the default value. 7.Update E14. 8.Set E12 as the default value. 9.Set D16 as the default value. BUG=b:220821454 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/brya/var/agah: Fix GPU GPIOsTim Wawrzynczak
While adding this train of patches to program the dGPU power sequences, I noticed some of the GPU GPIOs are incorrectly programmed in ramstage, so this patch fixes the settings. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-29mb/google/brya/var/felwinter: Update GPP_E19 from NF to NCJohn Su
Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-03-27mb/google/brya/var/banshee: Add mic mute switch settingFrank Wu
Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 00:13:56 +0000