diff options
| author | Terry Chen <terry_chen@wistron.corp-partner.google.com> | 2022-05-04 16:03:12 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-06 19:34:05 +0000 |
| commit | 3d5151968543127d3e89a15d25d1a0b6a150f571 (patch) | |
| tree | f2a9a7688b3eb19bb241827b6b82f48420f687b4 /src/mainboard/google/brya | |
| parent | 0405d8b3efa54ec2cdd9d6e07dc056d08c196145 (diff) | |
mb/google/brya/var/crota: Fix codec reset pin in overridetree
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the
reset pin to be deasserted in ramstage for proper power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/crota/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index a8b7113d99..b031eec9fa 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -132,7 +132,7 @@ chip soc/intel/alderlake device ref i2c0 on chip drivers/i2c/cs42l42 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)" register "ts_inv" = "true" register "ts_dbnc_rise" = "RISE_DEB_1000_MS" register "ts_dbnc_fall" = "FALL_DEB_0_MS" |