summaryrefslogtreecommitdiff
path: root/src/mainboard/google/brya
AgeCommit message (Collapse)Author
2021-02-18mb/google/brya: Remove `Some generic macros` commentAngel Pons
This comment is useless, and was dropped from the tree in the past. Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/brya: Add EC I/O decode windowsTim Wawrzynczak
BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15mb/google/brya: Enable cr50 supportTim Wawrzynczak
Add Kconfig options and devicetree entries for cr50 TPM. BUG=b:180017621 TEST=verify (via console) successful cr50 communications in verstage and payload (depthcharge). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-05mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAMTim Wawrzynczak
BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-01mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Change EC -> PCH wake pin to GPP_F17Boris Mittelberg
A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26mb/google/brya: Add memory DQ mapEric Lai
Add memory DQ map based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12mb/google/brya: Initialize overridetree.cbEric Lai
Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-12mb/google/brya: Add gpio tableEric Lai
Follow latest schematic to fill gpio table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-29Revert "mb/google/brya: Initiate peripheral buses"Felix Singer
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88. Reason for revert: Build bot fails. Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Initiate device treeEric Lai
Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Add EC smihandlerEric Lai
Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Set UART consoleEric Lai
Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/brya: Add flashmap descriptorEric Lai
BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/brya: Add new google brya mainboardTim Wawrzynczak
This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 21:04:14 +0000