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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-02-11 13:43:02 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-02-15 08:25:47 +0000
commitd4749184c242114ed2d43b2acdcbce9e568fe920 (patch)
tree4c82d815636a85215aa31d62d7b75f9bc1d1800d /src/mainboard/google/brya
parentad21d6bfcaa5fb5c5bd9cc34dee0c7ef8c85ea42 (diff)
mb/google/brya: Add EC I/O decode windows
BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/devicetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index b6b49dc361..c992f4fd2f 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -3,6 +3,12 @@ chip soc/intel/alderlake
device lapic 0 on end
end
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628