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path: root/src/mainboard/google/brya
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2023-12-19mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDDWeimin Wu
For EVT SCH: 1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera. 2. Delay reset for 5ms when device power on. BUG=b:312663347 TEST=1. Google Camera app working 2. Passed EA verified Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/nissa/var/anraggar: Disable SDCard controllerWeimin Wu
1. Anraggar doesn't support SDCard, so disable SDCard contorller. 2. Not disabling it will cause can't enter S0ix on first suspend. BUG=b:313585586 TEST=1. check lspci 2. can enter S0ix on first suspend Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-16mb/google/nissa/var/uldren: Reduce boot time for non-touchscreen skuDtrain Hsu
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s to under 1s. BUG=b:316434359 BRANCH=firmware-nissa-15217.B TEST=Boot time (cbmem -t) from 6,460,972 to 922,844 Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-12-15mb/google/brya: Enable FSP UPD LpDdrDqDqsReTrainingBora Guvendik
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong
The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-15mb/google/brya/var/dochi: Enable LpDdrDqDqsReTrainingMorris Hsu
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393,b:315739133 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14mb/google/nissa/var/anraggar: Update DTT settings for thermal controlWeimin Wu
Update DTT settings based on the suggestion of the thermal. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I2296990062cadc05202e3d1ab90af04234bda885 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)Weimin Wu
1. Ref to SCH, LTE use USB3 Port3, enable it. 2. Explicitly define the use of USB3 Port1 & USB3 Port2. BUG=b:315061146 TEST=can pass PCIe Hardware Compliance Test Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Change code style for register usb2_portsWeimin Wu
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11mb/google/nissa/var/quandiso: Tune P-sensorRobert Chen
Update proximity sensor tuning value from dedede/kracko tuning. Remove GPIO override to use the configuration from nissa baseboard: - GPP_B5 ==> SOC_I2C_SUB_SDA - GPP_B6 ==> SOC_I2C_SUB_SCL BUG=b:310050220 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthchargeWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged, keep mainboard C port to conn0. BUG=b:312998945 TEST=can boot from external Type-c USB disk Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Trim GPIO commentsWeimin Wu
Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.Weimin Wu
Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/nissa/var/anraggar: Fix Type-C & DP functionsWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165 Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Enable ILITEK touchscreenWeimin Wu
For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/brya/var/dochi: Update overridetree for type c1Morris Hsu
Update overridetree to correct AUX pin to USB-C port 3 BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/nissa/var/quandiso: Add LTE only daughterboard supportRobert Chen
Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shawn Ku <shawnku@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera deviceWeimin Wu
Enable MIPI camera for anraggar project. Sensor: OV13B10-GA5A Driver: DW9714V EEPROM: GT24P64E Ref to SCH, use MIPI 4-lane serial output interface. BUG=b:309518095 TEST=Google Camera app working Checking log with: coreboot log: \_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h kernel log: kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1 cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom cros_camera_service[4755]: Probing media device '/dev/media0' cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17) cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17 Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30mb/google/nissa/var/anraggar: Enable CNVi BluetoothWeimin Wu
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC, and the relevant configuration needs to be modified in overridtre.cb. BUG=b:304920262 TEST=lsusb ID 8087:0033 Intel Corp. rfkill list hci0:Bluetooth Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Tune eMMC DLL valuesSimon Yang
Anraggar cannot boot into OS and kernel loading failure. Update eMMC DLL values to improve initialization reliability - Sending different speed TX/RX command/data signal to eMMC and check the response is success or not. - Collecting every eMMC that use for the project - Based on above result to provide a fine tune DLL values BUG=b:308366637 TEST=Cold reboot stress test over 2500 cycles Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/brya/var/marasov: Update MSR Package Power Limit-1 valuesDaniel Peng
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION configSubrata Banik
This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards to retrieve the ISH version and store it into memory. Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms with ISH support (DRIVERS_INTEL_ISH). Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config selection for the Nissa baseboard is no longer needed. BUG=b:280722061 TEST=Able to build and boot google/marasov. Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory partsLeo Chou
Add taeko new supported memory parts in mem_parts_used.txt, generate spd-3.hex for these parts. 1. Samsung K4UBE3D4AB-MGCL 2. Micron MT53E1G32D2NP-046 WT:B BUG=b:312363368 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27mb/google/nissa/var/craask: Enable PIXA touchpadTyler Wang
Add PIXA touchpad for variants of craask. BUG=b:310489697 TEST=build craask firmware and test with PIXA touchpad Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-24mb/google/nissa: make GPP_F17 edge triggered to avoid spamming ECScott Chao
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level triggered and it causes AP (Application Processor) to keep sending GET_NEXT_EVENT to EC during resume from suspend by connecting AC. So we change GPP_F17 to edge triggered to avoid this condition. BUG=b:308716748 TEST=Original failure rate was 7 out of 10 times and it reduced to 0 out of 60 times on six joxer systems. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-23mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboardRobert Chen
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parametersVan Chen
The DPTF parameters were defined by the thermal team. Based on thermal table in 290705146#comment17. BUG=b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/google/nissa/var/joxer: Add speaker ldo configTerry Chen
Follow thermal validation, add ldo output select for speaker. BUG=b:297298847 TEST=emerge-nissa and deploy to DUT to verify audio functionality. Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas and brya0 variants. BUG=b:311740746 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify via "cbmem -c | grep HPS". Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-16mb/google/brya/var/osiris: Update power limit values for RPL CPUDavid Wu
Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/google/nissa/var/gothrax: Add GPIO configurationYunlong Jia
Add variant of LTE and WFC support on gothrax board. We base decisions on the values within the firmware configuration CBI field. In fw_config settings, if the board move LTE and WFC modules, the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7 pins need to be deasserted. BUG=b:303526071 TEST=emerge-nissa coreboot & \ Check against schematic. Whether it works as expected under different SKUs. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ia8041bdc599509911bde95d6294314036e75b227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-10mb/google/brya/Kconfig.name: Remove duplicate selectFelix Singer
That select is duplicate to the ones in the Kconfig file, and it shouldn't be there anyway. Remove it. Change-Id: I1a940f034a69f72280d15ab9a0c9d83f8111910e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78973 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09mb/google/nissa/var/gothrax: Add FW_CONFIG probe about DB/WFCYunlong Jia
Add FW_CONFIG probe to separate WFC settings. WFC_PRESENT/WFC_ABSENT Add FW_CONFIG probe for new DB_USB sku. DB_C_A_LTE/DB_A BUG=b:303526071 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brya/var/anraggar: Initialise overridetreewuweimin
Initialise overridetree based on the schematics revision 20231020A. Added data.vbt just only for running abuild completed. Real vbt define by CONFIG_INTEL_GMA_VBT_FILE in chromium:4936896. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I232bde990747be80e1ab62c3f0d010d5fc854cb5 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78456 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brya/var/anraggar: Add initial GPIOs configwuweimin
Configure GPIOs according to schematics revision 20231025G. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I7be6829fc27ee20e014c372d704333ebfd4967b8 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-04mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel moduleDaniel Peng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings on marasov. - WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW BUG=b:300045956 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-03mb/google/nissa/var/craaskov: Disable storage devices based on fw_configRex Chou
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-03mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to genericMatt DeVillier
Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02mb/google/brya/var/omnigul: Add fingerprint SPIJamie Chen
Add fingerprint SPI, and power off FPMCU during romstage. BUG=b:305860604, b:306320063 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-01mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-01mb/google/brya/var/quandiso: Add VBT data fileRobert Chen
Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT for quandiso as it has a VBT file now. The VBT file is copied from chromeos internal source and based on yaviks VBT. BUG=b:296506936 TEST=emerge-nissa coreboot Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2023-11-01mb/google/nissa: Add AUDIO_CONFIG in fw_configRen Kuo
The codec alc5650 has different setting from other amp codec in depthcharge. Since nissa has a single shared depthcharge target, add the fw_config field to allow different audio_configs. (refer to chromium:4983866) BUG=b:307410704 TEST=With depthcharge change, set fw_config and gbb flags on craaskana and check beep sound on firmware screen is workable. Change-Id: I7446fce57557204d91151f1a31755381c1813c6f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31mb/google/brya/var/*: Mark fingerprint reader as hiddenMatt DeVillier
Windows doesn't have / will likely never have a signed driver for the FPR, so set the device status as hidden so it will not appear as an unknown device in Windows Device Manager. Linux does not check/care about the ACPI device status. TEST=build/boot Win11 on google/brya (kano), verify FPR does not show up as unknown device under Device Manager. Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-29mb/google/brya/variants/craask: Enable DDR RFIM Policy for CraaskSumeet Pawnikar
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Craask variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=None BRANCH=None TEST=Build and boot Craask. - Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28mb/google/brya/var/dochi: Update overridetree for touchscreenMorris Hsu
Update overridetree for ILI2901 and eKTH7B18U touchscreen. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-10-27mb/google/nissa/var/joxer: Override tdp pl1 value for DTT tuningMark Hsieh
Follow thermal validation, override tdp pl1 in 6w ADL_N platform to 10w and override tdp pl1 in 15w ADL_N platform to 20w. BUG=b:307365403 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650 Reviewed-by: ChiaLing <chia-ling.hou@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-10-25devicetrees: Remove trailing backslash from multiline valuesFelix Singer
It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-24mb/google/brya: Set WWAN_PCIE_WAKE_ODL as interrupt on RedrixPaweł Anikiel
This signal gets deasserted by the WWAN modem to reactivate the PCIe link when in low power mode. In order to handle this efficiently, the kernel needs to set up an interrupt. BUG=b:301150499 TEST=Compiled and tested on google/redrix Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-23mb/google/brya/variants/anraggar: Generate 13 RAM IDswuweimin
Vendor DRAM Part Name Type MICRON MT62F512M32D2DR-031 WT:B LPD5 HYNIX H9JCNNNBK3MLYR-N6E LPD5 HYNIX H9JCNNNCP3MLYR-N6E LPD5 MICRON MT62F1G32D4DR-031 WT:B LPD5 HYNIX H9JCNNNFA5MLYR-N6E LPD5 MICRON MT62F2G32D8DR-031 WT:B LPD5 SAMSUNG K3KL6L60GM-MGCT LPD5x MICRON MT62F1G32D2DS-026 WT:B LPD5x SAMSUNG K3KL8L80CM-MGCT LPD5x HYNIX H58G56BK7BX068 LPD5x MICRON MT62F2G32D4DS-026 WT:B LPD5x SAMSUNG K3KL9L90CM-MGCT LPD5x HYNIX H58G66BK7BX067 LPD5x BUG=b:304920262 TEST=Run part_id_gen tool without any errors Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23mb/google/brya/var/dochi: Update overridetree for FingerPrintMorris Hsu
Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for TouchPadMorris Hsu
Update overridetree for TouchPad. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensorYunlong Jia
Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-20mb/google/brya/var/dochi: Enable EC keyboard backlightMorris Hsu
Enable EC keyboard backlight for dochi. BUG=b:299284564 TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/nissa/var/craaskov: Use runtime detection for touchscreensRex Chou
Use runtime detection for touchscreens. BUG=b:289962599 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia43ada8b3b6dbee95dbadacc353106e0f8f37549 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20mb/google/nissa/var/craaskov: Remove TOF functionRex Chou
Based on schematics and confirm with EE to remove TOF function. BUG=b:290891557 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/brya/var/dochi: update gpio settingsMorris Hsu
Configure GPIOs according to schematics revision 20231013. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I1ccab46b9f622fb98920d316c31800f39dc8ff95 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78384 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-17mb/google/brya: Create anraggar variantwuweimin
Create the anraggar variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:304920262 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANRAGGAR Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-16mb/google/nissa/var/quandiso: Update SD card GPIO settingsRobert Chen
Disable SD card GPIO with fw_config for quandiso units without SD card and pull GPP_H12 to high to match the spec. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2023-10-13mb/google/brya/var/dochi: Update overridetreeMorris Hsu
Update overridetree base on schematics revision 20230923. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/brya/var/dochi: use RPL FSP headersMorris Hsu
To support an RPL SKU on dochi, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL FSP headers. BUG=b:299570339 TEST=emerge-brya intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-10-13mb/google/nissa/var/quandiso: Update touchscreen power sequenceRobert Chen
Pull GPP_C1 to high in ramstage to meet touchscreen power sequence. BUG=b:302236370 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage & test touchscreen function on quandiso DUT Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-10mb/google/brya/var/dochi: update gpio settingsMorris Hsu
Configure GPIOs according to schematics revision 20230923. TEST=emerge-brya coreboot Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-10-09mb/google/nissa/var/joxer: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:303533832 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I575da55b96bf4deacec5c0992eae9930eb0745d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-09mb/google/nissa/var/joxer: Config I2C frequencyMark Hsieh
Measured the I2C frequency meets spec - I2C0 (TPM): 949.7 Khz - I2C1 (TouchScreen): 395.8 Khz - I2C3 (Audio): 387.4 Khz - I2C5 (Touchpad): 384.8 Khz BUG=b:303356736 TEST=USE="project_joxer emerge-nissa coreboot" and check all I2C devices measurement result Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I17dd1cb7800d00669f86fc6e2b350757695da881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78218 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-05mb/google/nissa/var/quandiso: Change camera fw_config feildRobert Chen
Quandiso reserve bit 11 for mipi camera usage. BUG=b:300574047 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/quandiso: Add ALC1019 amp supportRobert Chen
BUG=b:300573763 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Iff8167695c302f7b58976516d651a81f1a429bee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-05mb/google/nissa/var/uldren: Remove fw_config probe for TS and TPDtrain Hsu
When service center repair touchscreen or touchpad will change compatible device not specific one, the fw_config probe mechanism is not convenient for service center. Removing touchscreen and touchpad fw_config probe for the purpose. BUG=b:297840605 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77538 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ixSeunghwan Kim
Turn off GPP_H13 (EN_PP3300_SD_X) in s0ix for power saving. It reduces about 3mW of power consumption in s0ix on pirrha proto board. BUG=b:300845527 TEST=Built and verified GPP_H13 voltage was 0V in s0ix. Also verified SD card worked after s0ix for 20 times. Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04mb/google/brya/var/yavilla: Add VCM power control sequenceSerin Yeh
Add VCM power control to configure 2.8V and reset pin, and VCM can be powered on/off properly. BUG=b:292907385 TEST=Run ITS test Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/google/nissa/var/yaviks: Add probe in devicetree for USB C1/A0 portWisley Chen
Add probe fw_config to USB C1/A0 port on daught_board for DB_1A sku. BUG=b:294456574 TEST=emerge-nissa coreboot Change-Id: I2261b0e4d2b673b6186a435cce8dc6a4ccacb0a7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-03mb/google/brya: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1439f785cb9ceeefab9d24caa88e35bd43f68315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-29mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreenShon Wang
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. Support G2 TS have different slave address by fw_config BUG=b:295272539 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-28treewide: convert to tpm_result_tJon Murphy
Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to %#x hex printsJon Murphy
Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/nissa/var/craask: Correct the USB setting by fw_configRen Kuo
Modify the settings: 1)Add fw_config probe on USB type C for "DB_1C_LTE". 2)Add fw_config probe on USB type A for "DB_1A_HDMI". BUG=b:296791122 TEST=build and check USB functions on craask Change-Id: I2775098ab380995e62f264bc51a430762c256c4b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26mb/google/brya/var/dochi: Add memory configMorris Hsu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:298337185 BRANCH=firmware-brya-14505.B TEST=FW_NAME=dochi emerge-brya coreboot Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-26mb/google/nissa/var/pirrha: Add 4th DTT sensorSeunghwan Kim
Add 4th sensor device for DTT tuning. BUG=b:292134655 TEST=Built and verified DTT tool could monitor the new sensor device Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2023-09-25mb/google/brya: Add SOF driver entries for Nissa-based boardsMatt DeVillier
Facilitates correct profile selection by SOF Windows drivers. Profiles for nokris and quandiso will be added once correct board configs can be determined. TEST=build/boot Win11 on google/craask, verify correct audio profiles loaded, audio functional. Change-Id: Id4582b5dd74a4905ea509813ec99663577360095 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-09-25mb/google/brya/var/dochi: add generic LPDDR5 SPDs for DochiMorris Hsu
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Dochi: DRAM Part Name ID to assign MT62F1G32D2DS-023 WT:B 0 (0000) K3KL8L80CM-MGCT 1 (0001) H58G56BK8BX068 0 (0000) BUG=b:298337185 TEST=USE="project_dochi emerge-brya coreboot" Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-22mb/google/nissa/var/quandiso: Update USB port configRobert Chen
1. Support world facing usb camera on usb2_port7. 2. Update MB/DB fw_config to distinguish LTE and non-LTE devices. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Add P-sensor supportRobert Chen
- GPIO changes: GPP_B5 ==> I2C_P_SENSOR_SDA GPP_B6 ==> I2C_P_SENSOR_SCL GPP_H19 ==> P_SENSOR_INT_L - I2C SX9324 support - Disable GPIOs when sub board LTE not used BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-22mb/google/nissa/var/quandiso: Add SD card supportRobert Chen
GPIO changes - GPP_D8 ==> SD_CLKREQ_ODL - GPP_D17 ==> SD_WAKE_N - GPP_H12 ==> SD_PERST_L - GPP_H13 ==> EN_PP3300_SD_X Genesys Logic GL9750 support BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Disable WCAM supportRobert Chen
Quandiso doesn't support mipi WCAM. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Update initial files based on yavillaRobert Chen
Update files copied from yavilla - fw_config setting - GPIO setting - Kconfig setting - overridetree setting - SPD memory parts - variant setting BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage flash bin file in DUT Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/brya: Init TPM in bootblock when not using vbootMatt DeVillier
Brya queries the TPM in early ramstage (pre-device init) to determine if the CR50 has support for long-pulse interrupts. If the TPM (and underlying I2C controller) hasn't already been setup in verstage, it will fail to do so in ramstage since the I2C controller has not yet been initialized. To work around this, initialize the TPM in bootblock for the non-vboot case, to ensure the I2C controller is set up when needed in early ramstage. TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem console when initializing TPM in early ramstage. Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18drivers/tpm: Make temp test value naming consistentJon Murphy
Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-16mb/google/brya0: Configure _DSC for camera devicesBora Guvendik
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Boot to OS, check camera LEDs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-15mb/google/brya/var/craask: Disable C1 PMC mux conn for HDMIRen Kuo
Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn for HDMI. BUG=b:296791122 TEST=build and check HDMI function works on craaskana Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-09-15mb/google/brya/var/pujjo: modify wifi sar table for pujjo1eLeo Chou
1. WIFI_SAR_ID_4: AX211 2. WIFI_SAR_ID_5: AX203 (without WiFi-6E) BUG=b:293360900 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6c4705d25d927aaefbc8814ea1df3b4c36b30968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77790 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/brask/var/kuldax: Add fw_config probe for USB HubDavid Wu
Kuldax-refresh use USB Hub, add fw_config probe for USB Hub. BUG=b:275335023 BRANCH=brya TEST=Built and check firmware log. Change-Id: Ib983ca527a891718f317336597faad66d076247f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-13mb/google/brya: Create dochi variantMorris Hsu
Create the dochi variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:299570339 BRANCH=firmware-brya-14505.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_DOCHI Change-Id: Iadeb97bd217278cdf777ae350100313b4345ecf3 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77756 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/brya/var/craask: Add audio codec ALC5650Ren Kuo
Add audio codec ALC5650 related settings. BUG=b:289969623 TEST=emerge-nissa coreboot confirm the device in kernel log. Change-Id: I4b8a19e6248bd91cfc31feb84c6108413cd719e2 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77701 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/nissa/var/pujjo: Select VBT based on FW_CONFIG for pujjo1eLeo Chou
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG. BUG=b:299852789 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-13mb/google/brya/var/pujjo: modify fw_config to separate pujjo1e wifi sar tableLeo Chou
Use fw_config for a dedicated pujjo1e intel wifi sar table. BUG=b:293360900 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/nissa/var/craask: Modify SD_CARD element to prevent confuseTyler Wang
Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent confusion. Origin: 0 --> SD_GL9750S Modify: 0 --> SD_PRESENT BUG=b:296505165 TEST=emerge-nissa coreboot Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 18:40:30 +0000