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path: root/src/mainboard/google/brya/variants
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2023-06-17mb/google/nissa/var/gothrax: Generate RAM IDs for new memory partsYunlong Jia
Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:284388714 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-16mb/google/nissa/var/joxer: Disable storage devices based on fw_configMark Hsieh
- Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this. (it disables all probed devices when fw_config is unprovisioned.). - Removed `bootblock-y += variant.c` from Makefile.inc based on CL:3841120.(The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary.). BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-15mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPDRen Kuo
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-06-15mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NCLeo Chou
Pujjo does not support GPIO based D-SAR, so set GPP_D15 and GPP_H23 to NC. BUG=b:275264095 TEST=boot on pujjo and no impact WWAN dynamic SAR function Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/nissa/var/joxer: Add DmaProperty for ISHMark Hsieh
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on joxer. BUG=b:285477026 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/nissa/var/joxer: Remove fw_config probe for storage devicesMark Hsieh
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:285477026 TEST=On joxer eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/brya/variants/hades: Set WP signal to GPP_E12Tarun Tuli
Move the WP signal to GPP_E12 from the current GPP_E15 to match the design. BUG=b:285084125 TEST=WP signal reports as we expect Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-13mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-12mb/google/brya/var/hades: Abort power on if any rails fail to come upTarun Tuli
Currently if a rails PG fails to assert, the power on sequence continue after the 20ms timeout. Instead, we should abort and enter a power down. BUG=b:285980464 TEST=sequence now aborts and powers down on failure Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx railsMark Hsieh
This patch configures external V1p05/Vnn/VnnSx rails for Joxer to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:285477026 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-09mb/google/nissa/var/uldren: Modify WWAN power sequenceDtrain Hsu
Follow spec[1] to modify WWAN power sequence. The WWAN power sequence of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD reset when warm reset. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09mb/google/nissa/var/yavilla: Enable wifi SARShon Wang
Enable wifi sar function for yavilla/yavilly/yavijo. Use the fw_config to separate SAR setting for different wifi card. BUG=b:286141046 BRANCH=firmware-nissa-15217.B TEST=build, enabled iwlwifi debug, and check dmesg Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-09mb/google/brya/var/vell: Generate SPD ID for supported memory partShon Wang
Add new memory parts DRAM Part Name ID to assign Hynix H58G66AK6BX070 3 (0011) Hynix H9JCNNNFA5MLYR-N6E 4 (0100) Micron MT62F2G32D8DR-031 WT:B 4 (0100) BUG=b:279325772 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-08mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75716 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-07mb/google/brya/var/redrix: Add new GFX device with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-07mb/google/nissa/var/joxer: disable PCIE RP7Mark Hsieh
joxer removed SD card from all SKUs, thus disable pcie_rp7. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75658 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7Dtrain Hsu
Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-06mb/google/nissa/var/joxer: add lp5x SPDs for JoxerMark Hsieh
Add Makefile.inc to include four LPDDR5x SPDs for the following parts for Joxer: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) H58G56BK7BX068 4 (0100) MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) BUG=b:236576115 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibdc89c882581cfe4e5978faf4c6f70d653e0813d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75610 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04mb/google/brya/var/taeko: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/brya/var/marasov: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/constitution: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/kuldax: Enable Fast VMode for kuldaxDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I9ae58d704cba8124c6cb9865431aff84c9d154f7 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75600 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-03mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281950933 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-01mb/google/nissa/var/uldren: Add DPTF parametersDtrain Hsu
The DPTF parameters were verified by the thermal team. BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-05-31mb/google/nissa/var/uldren: Fine tune eMMC DLL settingsDtrain Hsu
Fine tune eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku. Change-Id: I82a55a1fe17aa910eb02464df463603dcbbbef05 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75459 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/nissa/var/uldren: Add ACPI DmaProperty for WLAN deviceDtrain Hsu
Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:279676191 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for lteDtrain Hsu
Use fw_config to probe lte. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5596f3536b0a21453f89e67615acabbbf6a8409b Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75337 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for touchpadDtrain Hsu
Use fw_config to probe touchpad. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib20abac74683c670c174821b821ede461dbb0163 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-24mb/google/hades: Enable smbus in device treeEric Lai
Hades uses the SODIMM, enable the smbus to see the SPD address for the memory. BUG=b:283138024 TEST=i2cdetect -l can see the smubs adapter. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/google/nissa/var/uldren: Add fw_config probe for touchscreenDtrain Hsu
Use fw_config to probe touchscreen. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5d8129b3af3aa09e5bc31160de82d9ef7af0dd59 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23mb/google/nissa/var/yavilla: Generate LP5 RAM ID for K3KL6L60GM-MGCTShon Wang
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-22mb/google/nissa/var/pujjo: Add WWAN_5G power on sequenceLeo Chou
Pujjoteen5 support WWAN 5G device, use variant.c to handle the power on sequence. BUG=b:279835626 TEST=Build and check WWAN 5G power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/google/nissa/var/yavilla: Config I2C frequencyTony Huang
Measured the I2C frequency meets spec 1. I2C0 (TPM): 976.1 Khz 2. I2C1 (TouchScreen); 394.0 Khz 3. I2C2 (WCAM); 377.9 Khz 4. I2C3 (Audio): 390.0 Khz 5. I2C5 (Touchpad): 389.3 Khz BUG=b:283374537 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check all I2C devices measurement result Change-Id: If6e3a4a2b1ac642561015a290e6579238c3c2b1b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-22mb/google/nissa/var/yavilla: Disable unused gpio with fw_configRobert Chen
Disable unused gpio for LTE daughter board, WFC and stylus. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc61321cd96a10dd34ff6cd9fcabe85a64bbfa9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75293 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19mb/google/nissa/var/yaviks: Generate LP5 RAM ID for K3KL6L60GM-MGCTWisley Chen
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:281928906 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia5193d3ab3d654f25d519ad9a954f2ca8a15a978 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75152 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@google.com>
2023-05-17mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device BUG=b:281943398 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-17mb/google/brya/variants/hades: Set up internal pull-up for GPIOsEran Mitrani
BUG=b:280843816 TEST=builds Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-15mb/google/brya/var/taniks: Update SOF speaker topologyMatt DeVillier
Taniks uses a 4-channel output config, rather than 2-channel. Update the SOF speaker topology accordingly. TEST=build/boot Win11 on taniks, verify speaker output functional. Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-14mb/google/nissa/var/uldren: Add wifi sar tableDtrain Hsu
Add wifi sar table for uldren BUG=b:279679700 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-14mb/google/hades: update TPM IRQ in early gpio tableEric Lai
TPM IRQ should be A20 not A13. RAM table is correct. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-12mb/google/nissa/var/uldren: Fix Touch screen power sequenceIan Feng
Based on touchscreen product spec. For uldren variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:279989974 TEST=Build and boot to OS in uldren. Touch screen is workable. Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-12mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli
Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-11mb/google/brya: Create gothrax variantYunlong Jia
Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11mb/google/brya/variant/hades: Reduce PEXVDD shutoff delay for HadesTarun Tuli
For the sequenced controlled shutdown path, there's a 10ms delay after the PEXVDD rail is disabled to permit discharge needed on Agah/Proxima. This can be dropped to 3ms for Hades designs Proto0 and forward. Once Agah board is dropped, "if CONFIG" can be cleaned up/removed. BUG=b:271167335 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08mb/google/brya: Split gma-mainboards for different baseboardsTarun Tuli
Allow different gma-mainboards configs for different baseboards as they support varying display interfaces. Set Brya to eDP only and Brask to HDMI only. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on both brya and brask varaints Change-Id: Iaf3f35b009d53e50723e4aa82c0f4932783f9bb9 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08mb/google/nissa/var/uldren: Update eMMC DLL settingsDtrain Hsu
Update eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 10 cycles of cold boot successfully Change-Id: I46e2f9df0e82e66fa3ae32aa87b4bcf30d5737ab Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/nissa/var/yavilla: Add G2touch touchscreen supportTony Huang
Update devicetree to support G7500 touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check touchscreen function Change-Id: I3b63b1bb45275ad7eef8799dcff27f264739c258 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/google/brya/var/marasov: Disable Tccold HandshakeFrank Chu
The patch disables Tccold Handshake to prevent possible display flicker issue for marasov board. Please refer to Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Boot to OS on marasov. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-04mb/google/brya: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on banshee and osiris variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-03mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPECJamie Chen
Tuning i2c frequency ,timing ,Waveform meet to SPEC i2c frequency : I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns. I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns. I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us. I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us. BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, EE check OK with test FW and TP function is normal. Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-05-01mb/google/nissa/var/craask: avoid camera LED blinking during bootJimmy Su
Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:274634319 TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior. Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7 Signed-off-by: Jimmy Su <jimmy.su@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27mb/google/nissa/var/yavilla: Add elan touchscreen supportTony Huang
Update devicetree to support ELAN I2C generic touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-26mb/google/brya/var/taeko: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taeko BUG=b:271003060 TEST= emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/brya/var/taniks: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taniks BUG=b:271003060 TEST=emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/brya/var/omnigul: Disable Tccold HandshakeDtrain Hsu
The patch disables Tccold Handshake to prevent possible display flicker issue for Omnigul board. Please refer to Intel doc#723158 for more information. BUG=b:279539826 BRANCH=firmware-brya-14505.B TEST=Verify the build for Omnigul board Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-25mb/google/nissa/var/yaviks: Update devicetree for UFC usb portTony Huang
USB port 6 connects to a USB front camera, it should always probe. Remove probe by rear camera fw_config. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-25mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIGTony Huang
Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 setting -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-22mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviksTony Huang
Yavilla board memory id setting references to yaviks. This CL aligen it with yaviks. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) H58G56BK7BX068 3 (0011) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/variants/hades: Swap LAN and SD Card PCIE PortsTarun Tuli
To aid in layout, the PCI ports for LAN and SD card were swapped. SD Card is now on RP3 (clksrc 4) LAN is now on RP8 (clksrc 3) BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gatingFrank Chu
The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/brya: Enable RTD3 root port mutex for WWANCliff Huang
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21mb/google/brya/var/marasov: Add _DSD object for wifiFrank Chu
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:278310435 BRANCH=firmware-brya-14505.B TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/brya/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. K4UBE3D4AB-MGCL BUG=b:267539938 TEST=run part_id_gen to generate SPD id Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-18mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHzJamie Chen
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Tuning i2c frequency for omnigul I2C0 - Audio CLK : 293.7khz I2C1 - TPM CLK : 388.8khz I2C3 - Touch Screen CLK : 294.8khz I2C5 - Touch Pad CLK : 389.2khz BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, and measure i2c clock. Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-17mb/google/brya/variants/hades: Update GPIO configsTarun Tuli
Update GPIO configs based on latest schematics (revision aabe36) Move GPP_D4->GPP_A13 (BT_DISABLE_L) Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD) Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL) BUG=b:269371363 TEST=builds Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-17mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFCTyler Wang
Add G2 touchscreen GTCH7503 for craaskino. Use SSFC to separate touchscreen settings. Bit 38-41 for TS_SOURCE: (1) TS_UNPROVISIONED --> 0 (2) TS_GTCH7503 --> 1 BUG=b:277979947 TEST=(1) emerge-nissa coreboot (2) Test on craaskino with G2 touchscreen (3) Test on craaskino with elan touchscreen Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I636f21be39f26a617653e134129a11479e801ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-13mb/google/nissa/var/yaviks: Update GPIOs to support yavillaShon Wang
Yavilla is a variant of yaviks which is almost identical to yaviks, so is reusing the yaviks coreboot variant. so update the GPIO tables to handle these based on fw_config. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I831b199055c931e7a4a393eeb9e75e83c8ae3c3a Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74264 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavillaTony Huang
Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG. BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74262 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavillaTony Huang
Yavilla will leverage yaviks FW build. It has one additional USB Type-A0 port, support stylus and support WWAN. Here update devicetree based on FW_CONFIG for yavilla's design. -Enable USB2 port3 and USB3 port1 for USB2/3 Type-A0 -Enable USB2 port5 and USB3 port3 for WWAN -Enable pen garage -Enable rear mipi cam -Enable Synaptics touchpad BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-12mb/google/nissa/var/yaviks: Generate SPD ID for new memory partsTony Huang
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. These new memory are added for yavilla. DRAM Part Name ID to assigna H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSxDtrain Hsu
This patch configures external V1p05/Vnn/VnnSx rails for Uldren to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11mb/google/brya/variants/hades: Update GPU power sequencing to add Hades supportTarun Tuli
Add GPU power sequencing changes for the Hades baseboard and variant. Some signals were added, moved or inverted. Based on implementation from Agah. Moved signals: GPIO_1V8_PWR_EN GPP_E11 GPIO_NV33_PWR_EN GPP_E2 GPIO_NV33_PG GPP_E1 New signals: GPIO_NV12_PWR_EN GPP_D0 GPIO_NV12_PG GPP_D1 Inverted signals: GPIO_FBVDD_PWR_EN GPP_A19 ifdef's will be dropped once the Agah variant is retired. BUG=b:269371363 TEST=builds and verified on Agah that DGPU is still detectable (lspci) Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-10mb/google/brya: Compile gpio.c in SMM when neededMatt DeVillier
Without gpio.c compiled in, SMMSTORE will fail to initialize and hang. Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE is selected. TEST=build/boot google/banshee with SMMSTORE support enabled Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-10mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C portDtrain Hsu
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. BUG=b:277149723 BRANCH=firmware-brya-14505.B TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u2 disabled Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ron Lee <ron.lee@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-10mb/google/brya/var/marasov: Configure Acoustic noise mitigationFrank Chu
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:271788117 TEST=build FW and system power on. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2023-04-04mb/google/brya/var/omnigul: Add ADL and RPL dptf settingsJamie Chen
Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul BUG=b:273415170 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-03mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_empMorris Hsu
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-03mb/google/brya/variants/hades: Add CPU power limitsTarun Tuli
Add CPU power limits support and values for RPL on Hades BUG=b:269371363 TEST=builds Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03mb/google/nissa/var/uldren: Add overridetreeVan Chen
Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-31mb/google/nissa/var/uldren: Update gpio settingsVan Chen
Configure GPIOs according to schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id414c9b0d94faffd2d71c348fc7146a6101196e9 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-31mb/google/brya/variants/hades: Add initial GPIO config for hades boardTarun Tuli
Initial hades GPIO config. Combination of original brya basebaord, Agah and new arbitrage output for hades design. Also moved GPIO config to the non baseboard variant model as we did on rex0. BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-30mb/google/nissa/var/yavilla: Disable storage devices based on fw_configTony Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-30mb/google/nissa/var/yavilla: Update devicetree settingTony Huang
Update devicetree according to yavilla's design. Add Kconfig for TPM I2C bus. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1b44436a7f93d62764d0451c738ae33976a24a15 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-03-29mb/google/brya/var/crota: Add lp5x memory parts for `K3KL6L60GM-MGCT`Terry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign K3KL6L60GM-MGCT 5 (0101) BUG=b:267249674 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-29mb/google/nissa/var/yavilla: Update GPIO settingShon Wang
Configure GPIOs according to schematics. BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I5a522b59468667d20674d55597cc06975bc12ab5 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2023-03-27mb/google/brya/var/omnigul: Add WIFI SAR tableJamie Chen
Add WIFI SAR table for omnigul. BUG=b:273170023,b:273652516 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I2db057371754961503cfdc59f21c365fc82672c4 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73940 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-26mb/google/brask/var/constitution: Add TcssAuxori for constitutionMorris Hsu
Enable SBU orientation handling by SoC for both USBC port2 and USBC port3. Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't, they do not flip the data lines, hence we need to set bits for USBC ports. Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-23mb/google/brya/var/taeko: Correct comments to prevent confusionJoey Peng
The PCIE RP 9 on taeko is for eMMC. Correct the comments to prevent confusion. BUG=b:271003060 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-22mb/google/hades: Add variant device treeEric Lai
Follow 03_16 schematic to add the device tree. BUG=b:272816611 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85a05fec816954fd3408feccae84e0b9860ecdc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73838 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-22mb/google/hades: Remove gspi from baseboard device treeEric Lai
GSPI is not used, remove it. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I55d3f5119bc502621bdeae63b3d1e4cf43582038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-17mb/google/nissa/var/uldren: Create RAM ID tablevan_chen
DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3KL6L60GM-MGCT 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) K3KL8L80CM-MGCT 2 (0010) H58G56BK7BX068 2 (0010) BUG=b:270103716 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia53c2be2ec606f42ac8bca06103b028e62ae6dbc Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-17mb/google/nissa/var/yavilla: Generate SPD ID for supported memory partsTony Huang
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56BK7BX068 1 (0001) MT62F1G32D2DS-026 WT:B 1 (0001) K3KL8L80CM-MGCT 1 (0001) H58G66BK7BX067 2 (0010) MT62F2G32D4DS-026 WT:B 2 (0010) K3KL9L90CM-MGCT 2 (0010) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I82919919ec33d6bf9d86132490df754873b5df88 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17mb/google/brya: Create yavilla variantTony Huang
Create the yavilla variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVILLA Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17mb/google/brya/var/omnigul: Update RAM ID tableJamie Chen
Add new ram_id:0010 for Micron MT62F1G32D2DS-023 WT:B. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H58G56BK8BX068 2 (0010) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:273138520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Idc08624469590096047e5f77fb2e4ffb733f09ec Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73726 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-16mb/google/brya/var/taniks: Remove unused temp sensor settingJoey Peng
Rwmove temp sensor 3 for taniks since we do not use it. BUG=b:265075696 TEST=emerge-brya coreboot, flash to DUT and will not see error messages Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-16mb/google/brask/var/aurash: Allow USB2/3 wakeups to (un)plug events in dtZoey Wu
BUG=b:271373437 BRANCH=none TEST=Verify USB-A device could wake up Aurash. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I67fc02d6c5660e0e3d1ab95bbda8ace1dc14b524 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73414 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15mb/google/brya/var/omnigul: Correct mux_conn for USB C1Dtrain Hsu
Modify USB C1 mux_conn to 1. It should match ec settings. BUG=b:272394875, b:272667290 BRANCH=firmware-brya-14505.B TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi. Change-Id: I61b77405d1790b044174cef954e5bf910141f424 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-29 03:45:12 +0000