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path: root/src/mainboard/google/brya/variants
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2021-06-18mb/google/bry: remove GSC option as it's not usedYH Lin
BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I932178dc395a4a96682a2e2076131feb3342aa52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55597 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya/brya0: Update GPIO tables based on new board revTim Wawrzynczak
This change also restores GPIOs to their proper settings for prior board revs. BUG=b:189362981 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325 Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya: Configure WWAN GPIO earlyVarshit Pandya
In order to meet timing requirement of WWAN reseting it in early GPIOs and asserting Reset GPIO in ramstage BUG=b:180166408 TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/brya: Create gimble variantMark Hsieh
Create the gimble variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190334274 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GIMBLE Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10mb/google/brya: Add variant GPIO override functionsTim Wawrzynczak
Provide functions to allow for variants to override only a few pads from the baseboard table. BUG=b:189362981 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ae6c11ca8614d523f3402f1c1abb7c82124e473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-07soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar
Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-06-07mb/google/brya: Add EC_HOST_EVENT_USB_MUXJohn Zhao
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source. BUG=None TEST=Build coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6f4dcbc60a6cb131f28de205bd9ef436f2b508eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55126 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/google/brya: Remove I2C4 usage in devicetree.cbSubrata Banik
I2C4 is not used pn Brya hence make below changes: 1. Disable it in SerialIoI2cMode. 2. Remove I2C4 config in common_soc_config. TEST=Make sure FSP is not programming I2C4. Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04mb/google/brya: Add firmware configuration probing for audioSugnan Prabhu S
For all of the audio devices in overridetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682 BUG=b:188696010 TEST=test different audio devices based on fw_config value: > AUDIO=UNKNOWN ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000200 4 2 Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04mb/google/brya/brya0: Fix irq and CS lines for FPMCUTim Wawrzynczak
The entries in the ACPI tables for the fingerprint module's SPI configuration were incorrect. 1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be described by Interrupt(), not GpioInt() 2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on` BUG=b:181635081 TEST=verified in kernel logs: localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi' [ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected [ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03mb/google/brya: Create primus variantScott Chao
Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Hynix H9HCNNNCPMMLXR-NEE 2) Micron MT53E1G32D2NP-046 WT:B BUG=b:186616388, b:181736400 Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54951 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03mb/google/brya: move MIPI camera setting into overridetreeScott Chao
In order to support no MIPI camera variant, move related configuration into variant folder. BUG=b:188272162 BRANCH=none TEST=build no MIPI camera variant without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-01mb/google/brya: Enable WFCMeera Ravindranath
1. Add 1 port and 1 endpoint 2. Add support for OVTI8856 WFC is on I2C0 BUG=None BRANCH=None TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnectmadhusudanarao amara
Enabling AC connect/disconnect wake events in brya to meet Chrome OS wake requirements. These changes are similar to Volteer and Shadowmountain. BUG=none BRANCH=None TEST=manual tested DUT wakes for AC connect/disconnect in S0ix Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35 Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE"Tim Wawrzynczak
This reverts commit 2f8a7046bb120d96022ada1e74545f859f97521f. Reason for revert: CB:54752 makes this unnecessary Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21mainboard/google/brya: Add SCI event EC_HOST_EVENT_USB_MUXmadhusudanarao amara
Send USB_MUX host event for the connect/disconnect type C devices. BUG=none BRANCH=None TEST=manual tested USB connect/disconnect Change-Id: I5a720e1f1ea42f200e0e4c98f42894e4b92c67f8 Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54725 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19mb/google/brya/brya0: Manually probe fw_config for DB_LTETim Wawrzynczak
In order to use the USB WWAN module in USB mode (as opposed to PCIe), the PCIe RP must be turned off at the FSP level. The `probe` statement in the devicetree unfortunately takes effect too late, because the UPDs for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas fw_config probing for devicetree is done in ramstage. Add a new variant-specific file which will handle manually setting the UPD based on FW_CONFIG instead. BUG=b:180166408 TEST=set CBI FW_CONFIG field to LTE_USB, see message in console, set field to LTE_PCIE, do not see message in console. Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Disable dynamic GPIO PM for community 3Maulik V Vaghela
We recently added GPIO definition for PCIE vGPIO for Alder Lake. We also need to disable GPIO dynamic PM for this community which is already done for other communities as well. BUG=b:188392183 BRANCH=None TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also disabled Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6Eric Lai
PCIE6 only needed when use the PCIE LTE. BUG=b:180166408 BRANCH=none TEST=FM350 can/can't be detected when enable/disable this config. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/brya: Add the first FW_CONFIG fields to brya0Tim Wawrzynczak
1) USB sub-board 2) SD sub-board 3) GSC 4) Keyboard backlight 5) Audio sub-board 6) LTE module Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13mb/google/brya: enable DPTF functionality for bryaSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=b:188028732 TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29mb/google/brya: Enable ELAN9050 touchscreenEric Lai
Enable ELAN9050 touch screen. Follow below spec: eKTH7913U_eKTH7915U_eKTH7918U_Product Spec_V1.0_20200807 IPM-11 BUG=b:186342801 TEST=touchscreen is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I4c247fae33b9178c8706552aba2f950c9a674ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29mb/google/brya: Adjust WWAN power sequenceEric Lai
Follow L850GL spec to adjust power sequence. RST need to drive low before power on then drive to high. SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8 BUG=b:186374631 TEST=WWAN is detected by lsusb. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/google/brya: remove WLAN PCIE settingEric Lai
Brya uses CNVi WiFi module, PCIE setting is not required. TEST=WiFi is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22mb/google/brya: Enable display and DSP audio UPDSugnan Prabhu S
This patch includes changes to enable display and DSP audio UPD. BUG=b:181219097,b:183482000 TEST=Audio sound card is detected and listed by the linux kernel. Audio playback and capture is working on the Brya. Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-16mb/google/brya: Configure TCSS OC pins for bryaMaulik V Vaghela
TCSS OC pins has not been correctly configured for brya. This patch fills the value from devicetree to correct the OC pins mapping BUG=b:184653645 BRANCH=None TEST=check if UPD value has been reflected correctly Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-15mb/google/brya: Add FPMCU power controlEric Lai
Enable CRFP power control in gpio table. RST needs to drive low before PWR enable. Since reset signal is asserted in bootblock, it results in FPMCU not working after a S3 resume. This is a known issue. BUG=b:181377402 BRANCH=None Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10mb/google/brya: Change GPP_E16 default to highAlex Levin
To enable WWAN we want to release it from reset start. BUG=b:180166408 TEST=WWAN enumerates on brya Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52199 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/brya: Change GPP_D15/D16 default to lowEric Lai
WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05mb/google/brya: Enable south XHCI ports 1 and 2Furquan Shaikh
FSP v2081 has a bug where it uses the information about south XHCI ports to enable TCSS XHCI ports. This change works around this bug by enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0 already enables south XHCI port 1 in overridetree.cb, however, it is still enabled in baseboard/devicetree in case more variants are added to brya before FSP is fixed. BUG=b:184324979 TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled. Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02mainboard/google/brya: Disable touchpad as S3 wake sourceBoris Mittelberg
This change disables touchpad interrupt, as it sends spurious wake signal via GPP_F14 and immediately wakes the system from S3. It happens because touchpad's power is gated by deassertion of PLTRST#. The behaviour for S0ix is unchanged. BUG=183738135 TEST=manually Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51831 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mainboard/google/brya: Enable tight timestampBoris Mittelberg
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for CREC device BUG=none TEST=manual test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEPBoris Mittelberg
PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured to reset state on PLT reset assertion. This change reconfigures the pad using DEEP instead of PLTRST to retain pad configuration across S3. BUG=b:178545523 TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake source is GPP_F17 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-26mb/google/brya: Update ddr configSubrata Banik
Fixed ddr config to override the FSP default value. BUG=b:182772421 TEST=Built image and passed memory training. Without this change: RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 } With this change: RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 } Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22mb/google/brya: Enable S0ixSugnan Prabhu S
This change enables S0ix for brya platform. BUG=b:181843816 TEST=Built image and booted to kernel. Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Remove BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-09mb/google/brya: Define ChromeOS GPIO support in ACPI tbalesTim Wawrzynczak
Define the ChromeOS GPIOs (physical write-protect and virtual recovery mode) in ACPI tables so the OS knows which physical pad is used for them. BUG=b:181887865 TEST=flashrom_tester is able to "see" the WP GPIO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3feed366afd6507894a1d31304891cc785a4d314 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51347 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08mb/google/brya: Finish support for ChromeOS GPIOsTim Wawrzynczak
BUG=b:181887865 TEST=`crossystem` shows correct state of WP signal when toggled Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-06mb/google/brya: Move GPE configuration to baseboard/devicetree.cbFurquan Shaikh
This change moves GPE configuration from brya0/overridetree.cb to baseboard/devicetree.cb since all variants will end up using the same configuration. TEST=Verified using "abuild -p none -t google/brya -b brya0 --timeless" that coreboot.rom generated with and without this change is the same. Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05soc/intel/adl, mb/google/brya: Add IPU to devicetreeTim Wawrzynczak
BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05mb/google/brya: brya0: Add ACPI support for Type-C portsTim Wawrzynczak
BUG=b:181160586, b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/brya: fix BT enumeration issueAamir Bohra
Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/brya: Fix a few mistakes in brya0 overridetreeTim Wawrzynczak
1) Both SAR sensors had a UID of `2`, making them indistinguishable 2) No `device` underneath max98357a `chip` Change-Id: Icf586229532819a7779652cbee73755b036dfbdc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/brya: Fix chip driver and HID for Cr50 TPMTim Wawrzynczak
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully register the device with its driver. Change to GOOG0005 to match other ChromeOS devices with I2C-connected Cr50 TPM. BUG=b:180657076 TEST=abuild Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18mb/google/brya: Enable MLB USB Type-A PortTim Wawrzynczak
The USB Type-A port on the MLB was added to the schematic at the last minute and it was missed when adding brya0's overridetree. Also fix a few USB ACPI entries. BUG=b:180403898 TEST=`lsusb` shows plugged-in flash drive Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15mb/google/brya: Add EC I/O decode windowsTim Wawrzynczak
BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15mb/google/brya: Enable cr50 supportTim Wawrzynczak
Add Kconfig options and devicetree entries for cr50 TPM. BUG=b:180017621 TEST=verify (via console) successful cr50 communications in verstage and payload (depthcharge). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-05mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAMTim Wawrzynczak
BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Change EC -> PCH wake pin to GPP_F17Boris Mittelberg
A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-26mb/google/brya: Add memory DQ mapEric Lai
Add memory DQ map based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12mb/google/brya: Initialize overridetree.cbEric Lai
Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-12mb/google/brya: Add gpio tableEric Lai
Follow latest schematic to fill gpio table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-29Revert "mb/google/brya: Initiate peripheral buses"Felix Singer
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88. Reason for revert: Build bot fails. Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Initiate device treeEric Lai
Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/brya: Add new google brya mainboardTim Wawrzynczak
This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 10:33:34 +0000