Age | Commit message (Collapse) | Author |
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A new schematic revision indicates that the old wake pin is not used,
and brya will only use 1 IRQ pin from EC, routed to GPP_F17
BUG=b:178605367
TEST=Build test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Follow latest schematic to fill gpio table.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock and ramstage.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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