| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-04-05 | mb/google/brya: Enable south XHCI ports 1 and 2 | Furquan Shaikh |
| 2021-03-22 | mb/google/brya: Enable S0ix | Sugnan Prabhu S |
| 2021-03-15 | mb/google/brya: Remove BT PCI interface and add BT flag | Cliff Huang |
| 2021-03-06 | mb/google/brya: Move GPE configuration to baseboard/devicetree.cb | Furquan Shaikh |
| 2021-03-05 | soc/intel/adl, mb/google/brya: Add IPU to devicetree | Tim Wawrzynczak |
| 2021-02-22 | mb/google/brya: Fix chip driver and HID for Cr50 TPM | Tim Wawrzynczak |
| 2021-02-15 | mb/google/brya: Add EC I/O decode windows | Tim Wawrzynczak |
| 2021-02-15 | mb/google/brya: Enable cr50 support | Tim Wawrzynczak |
| 2021-02-05 | soc/intel/alderlake: Refactor PCIE port config | Eric Lai |
| 2021-02-01 | mb/google/brya: Initiate peripheral buses | Eric Lai |
| 2020-12-29 | Revert "mb/google/brya: Initiate peripheral buses" | Felix Singer |
| 2020-12-29 | mb/google/brya: Initiate peripheral buses | Eric Lai |
| 2020-12-04 | mb/google/brya: Initiate device tree | Eric Lai |
| 2020-11-22 | mb/google/brya: Add new google brya mainboard | Tim Wawrzynczak |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
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