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2018-07-25mb/google/x86-boards: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04mb/google: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/superio: Rename global control devices as SUPERIO_DEVElyes HAOUAS
Use SUPERIO_DEV for global control device instead of DUMMY_DEV. Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25852 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-25google/beltino: fix LED polarity for mccloud variantMatt DeVillier
The LED polarity was set incorrectly, fix using values derived from original Chromium sources: branch firmware-mccloud-5827.B, ToT src/mainboard/google/mccloud/smihandler.c src/mainboard/google/mccloud/romstage.c TEST: boot google/mccloud, observe power LED on normally, blinking in S3/S4, and off in S5. Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24Update files with no newline at the endMartin Roth
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-06mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I1f906c8c465108017bc4d08534653233078ef32d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-31google/beltino: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. All beltino variants use the exact same USB port layout. Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-01acpi: fix FADT header version for ChromeOS devicesMatt DeVillier
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices' FADT version were incorrectly set to 3, rather than the correct ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these devices reporting compliance to ACPI 2.0, rather than ACPI 3.0. This mirrors similar recent changes to SKL and APL SoCs. Test: boot any affected device and check ACPI version reported vai FADT header using OS-appropriate tools. Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08google/beltino, tidus: simplify led_power_on() functionMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Remove unnecesary function param, includes for Tidus. Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17744 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07google/beltino: fix LED, simplify function for Tricky variantMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Fix non-off LED polarity for Tricky using correct value from Chromium source TEST: power on Tricky, observe LED lit / solid Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-24Add Haswell Chromeboxes/Chromebase using variant board schemeMatt DeVillier
Combine existing board google/panther with new ChromeOS devices mccloud, monroe, tricky, and zako, using their common reference board (beltino) as a base. Chromium sources used: firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...] firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.] firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...] firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...] Existing google/panther board will be removed in a subsequent commit. Variant setup modeled after google/reef Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17329 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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