coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-12-19	mb///early_init.c: Remove unused <device/pci_{def,ops}.h>	Elyes HAOUAS
2019-11-23	Kconfig: comply to Linux 5.3's Kconfig language rules	Patrick Georgi
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-11-04	mb//{i82801gx}: Use sb/intel/common/acpi/platform.asl	Arthur Heymans
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-05-25	nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
2019-04-23	src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config	Arthur Heymans
2019-03-13	src/mainboard///cstates.c: Drop unused includes	Elyes HAOUAS
2019-03-08	src/mb: Shorten 'include <arch/x86/include/arch/acpigen.h>'	Elyes HAOUAS
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-07	src: Remove unused include device/pnp_def.h	Elyes HAOUAS
2019-01-23	nb/intel/pineview: Use parallel MP init	Arthur Heymans
2019-01-14	nb/intel/pineview: Move the boilerplate mainboard_romstage_entry	Arthur Heymans
2019-01-09	cpu/intel: Use the common code to initialize the romstage timestamps	Arthur Heymans
2019-01-08	sb/intel/i82801gx: Autodisable functions based on devicetree	Arthur Heymans
2019-01-08	mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6	Arthur Heymans
2019-01-03	mb/foxconn/d41s: Program the subsystemid	Arthur Heymans
2018-12-28	arch/x86: Drop spurious arch/stages.h includes	Kyösti Mälkki
2018-11-23	mb: Set coreboot as DSDT's manufacturer model ID	Elyes HAOUAS
2018-11-21	ACPI: Fix DSDT's revision field	Elyes HAOUAS
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
2018-09-13	src/mainboard//: Set Mini-ITX boards' category to "mini"	Angel Pons
2018-08-23	mb/foxconn/d41s: Add mainboard	Arthur Heymans