| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-11 | memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere | Patrick Georgi |
| 2020-12-02 | cbfs: Enable CBFS mcache on most chipsets | Julius Werner |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-04 | mainboard/emulation: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | mainboard/[a-f]*: Remove copyright notices | Patrick Georgi |
| 2019-12-11 | fmap: Make FMAP_CACHE mandatory if it is configured in | Julius Werner |
| 2018-04-27 | RISC-V boards: Remove PAGETABLES section from memlayout.ld | Jonathan Neuschäfer |
| 2016-10-24 | RISCV: Clean up the common architectural code | Ronald G. Minnich |
| 2016-06-21 | riscv-spike: Move coreboot to 0x80000000 (2GiB) | Jonathan Neuschäfer |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-09-16 | riscv-memlayout: fix existing memlayout issues, add sbi interface | Thaminda Edirisooriya |
| 2015-08-09 | riscv-spike: support for Spike emulation of riscv | Thaminda Edirisooriya |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |