coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-12-30	intel CAR: Fix DCACHE_RAM_BASE for old sockets	Kyösti Mälkki
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2012-02-17	intel/82801dx: Move HAVE_HARD_RESET to southbridge	Patrick Georgi
2011-10-28	Get rid of the old romstage-as-bootblock ROM layout	Patrick Georgi
2010-12-08	Move "select CACHE_AS_RAM" lines from boards into CPU socket.	Uwe Hermann
2010-08-30	We call this cache as ram everywhere, so let's call it the same in Kconfig	Stefan Reinauer
2010-08-30	Restructured all vendors' Kconfig files to no longer source the boards'	Jens Rottmann
2010-08-03	Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /	Stefan Reinauer
2010-07-06	Re-integrate "USE_OPTION_TABLE" code.	Edwin Beasant
2010-04-11	The ADL855PC was never confirmed working (in fact it's pretty sure that code	Stefan Reinauer
2010-03-17	more warning fixes.	Stefan Reinauer
2010-02-27	This does the following:	Stefan Reinauer
2010-02-25	Drop i855pm port and rename i855gme to i855 instead.	Stefan Reinauer
2010-02-09	Move all the copies of the romstage.inc rule to	Patrick Georgi
2010-01-25	Fix ACPI build on a couple of boards (now that it's active)	Patrick Georgi
2010-01-25	More Kconfig changes to improve match with newconfig:	Patrick Georgi
2009-10-28	Fix some builds with Kconfig.	Myles Watson
2009-10-26	Define some variables that were not defined. There are a couple left.	Myles Watson
2009-10-24	Major cleanups of the hard_reset() code and config in coreboot.	- supermicro/x6dhe_g/auto.c
2009-10-20	Fix all board names in Kconfig as per wiki / vendor website.	Uwe Hermann
2009-10-16	Set default ROM sizes per-board to match the ROM chip that came	Uwe Hermann
2009-10-09	Remaining boards are Kconfig'd now. Whether they work	Patrick Georgi