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Now that the USB configs are in the devicetree, only the
bootblock_mainboard_early_init function remains in early_init.c. It is
identical between every variant except the E6230, which enabled fewer
decode ranges in the LPC_EN register. Enabling the additional decode
ranges probably shouldn't cause issues, so go with the majority.
TEST=Timeless builds do not change with the exception of the E6230.
Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h
instead of magic numbers, as well as the enums for each of the register
field values. The macros were generated by running util/hda-decoder
against the original azalia logs used for the original board ports.
TEST=Timeless builds for all variants did not change between main
and this patch
Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This was adapted from CB:22693 from Iru Cai, which was based on
autoport. I do not physically have this system. Someone with physical
access to an E6230 running version A11 of the vendor firmware sent me
the VBT after running the command `intelvbttool --inlegacy --outvbt
data.vbt`. This new version of the port has not yet been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82153
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is QAL70/LA-7741P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is codenamed Vida. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. The VBT was obtained using
intelvbttool while running version A14 (latest available version) of the
vendor firmware.
Tested and found to boot as part of a libreboot build based on upstream
coreboot commit b7341da191 with additional patches, though these do not
appear to affect SNB/IVB. The base E6430 patch was tested against
coreboot main.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is PAL70/LA-6611P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A22 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is Krug 14". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A02 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is Krug 15". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A14 of the vendor firmware.
This was originally tested and found to be working as a standalone
board port in Libreboot, but this variant based port in upstream
coreboot has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82126
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port.
I was also sent the vbios obtained using intel_bios_dumper while running
version A22 of the vendor firmware, which I then processed using
`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt.
This was originally tested and found to be working as a standalone board
port in Libreboot, though this variant based port in upstream coreboot
has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor mainboards' code to use the new GPIO driver.
TEST=Put Google Jecht to S3 sleep and check if the LED blinks.
Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix potential undefined behaviour in the `get_pkg_power()` function:
- If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is
invalid
- If `rapl_power_unit > 7`, the result of the shift doesn't fit into a
`uint8_t`
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).
The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.
Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environment control
- GPIOs
- S3 Sleep mode
- WakeOnLan
Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree) and earlier commits, the USB port configuration
should be located in the devicetree instead of the mainboard_usb_ports
array, typically located in the boards early_init.c.
TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and
USBOCM2 RCBA registers in the inteltool dump did not change between
an E6430 build before and after the sb/intel/bd82x6x that moved the
usb config to the devicetree.
Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Physical DP ports are DP2/DP3 (HDMI2/HDMI3 for DP++)
- VGA port is Analog
- DP1 is not connected
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I8ed79167d5445d607acbee491c3382ff2585583f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Based on autoport output.
It boots to Arch Linux (Linux 6.6.3) from USB and mSATA with SeaBIOS.
Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was
not tested. This is based on the autoport output with some manual fixes.
The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt`
while running version A24 (latest version) of the vendor firmware.
The flash is 8MiB + 4MiB, and can be easily accessed by removing the
keyboard. It can also be internally flashed by sending a command to the
EC, which causes the EC to pull the FDO pin low and the firmware to skip
setting up any chipset based write protections [1]. The EC is the SMSC
MEC5055, which seems to be compatible with the existing MEC5035 code.
Working:
- Libgfxinit
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
right side is HCD index 1) with the CH347
- Keyboard
- Touchpad/trackpoint
- ExpressCard (tested with USB 3.0 card)
- Audio
- Ethernet
- SD card reader
- mPCIe WiFi
- SeaBIOS 1.16.3
- edk2 (MrChromebox's fork, uefipayload_202309)
- Internal flashing using dell-flash-unlock
Not working:
- S3 suspend: Possibly EC related, DRAM power is getting cut when
entering S3
- Physical wireless switch: this triggers an SMI handler in the vendor
firmware which sends commands to the EC to enable/disable wireless
devices, and has not been reimplemented
- Battery reporting: needs ACPI code for the EC
- Brightness hotkeys: probably EC related
- The system reports that the power button was pressed and shuts down
when the CPU hits around 86 degrees Celsius, before the CPU can
thermal throttle. Likely EC and possibly PECI related.
- Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB
initializes the 8042 PS/2 controller in a way that is incompatible
with how the EC firmware emulates it. GRUB tries to initialize the
controller with scan code set 2 without translation, but the EC only
ever returns set 1 scan codes to the system and thus is only works as
an untranslated set 1 keyboard or a translated set 2 keyboard,
regardless of commands to set the scan code. A USB keyboard works
fine.
Unknown/untested:
- Dock
- eSATA
- TPM
- dGPU on non-UMA model
- Bluetooth module (not included on my system)
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77444
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For mainboards using southbridge/intel/bd82x6x, copy the contents
of mainboard_usb_ports array into southbridge devicetree. In-line
comments are maintained.
Boards also capable of using MRC raminit are done in a separate
patch.
Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the
same value and conveys additional information to the reader. Done with a
bulk search and replace operation.
Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.
The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 1.
Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.
This was tested to make fan control work on my OptiPlex 7020 SFF.
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These machines come with a TPM1.2 device by default. It is somewhat
obsolete these days, but there is no harm in enabling it.
Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously incorrect sets of SATA ports were enabled.
There are no publically available schematics, but I am almost certain
the new values are correct.
The original 0x33 value was carlessly copy pasted, and only enables
ports 0, 1, 4, 5, leaving 2, 3 disabled.
On the SFF, with 0x33 only the first 2 ports worked. I have verified
by plugging in devices under the stock firmware that 0, 1, 2 are the
ones that should be enabled, so setting the value to 0x7 per datasheet.
This was also tested in practice to work.
I don't have an MT, but I was told the two white ports didn't work
with 0x33, so those are most certainly ports 3, 4, hence me setting
the value to 0xf. If the MT's working ports are port 0, 1 on the PCH
this is correct.
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The OptiPlex 7020 and 9020 use physically identical motherboards.
WARNING: PWM fan control doesn't work via the EC and the fan runs at a
fixed speed. There is likely more EC init to reverse engineer.
Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT
(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
mic inputs untested
- Ethernet: tested, works
(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55232
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Since all devicetrees from dell/snb_ivb_workstation are using the
reference names for PCI devices now, remove the equivalent comments
documenting their function.
Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I80bd87aa2f97da74a1bbcf05b16f0d5980e142f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Based on the schematic and vendor ASL code, PCI interrupt lines ABC of
the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC.
From lspci and the schematic this chip is PCI device 1. The original
config copied from the T400 was routed ABCD->BCDA, causing Linux to
issue an "irq 18: nobody cared" message when inserting an SD card.
This is fixed by this patch and the SD card now works properly.
Change-Id: Iede1de72d5369f1aebbac170792733739add3431
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Mainboard name is Compal JBL00. This is based on the GM45/ICH9M chipset
and uses DDR2 RAM. The EC is a SMSC MEC5035 which has internal flash, so
there's no issue about making sure to include the EC firmware in the
BIOS region. This only supports the variant with integrated graphics
only, the version with a discrete Nvidia Quadro NVS 160M is not
supported.
This port was based on the Lenovo T400 port.
Working:
- USB EHCI debug (lower USB port on right side)
- Keyboard
- Touchpad/trackpoint
- VGA
- Displayport
- ExpressCard
- Audio
- Ethernet
- mPCIe WiFi
- mPCIe Bluetooth (uses USB)
Not working:
- Brightness hotkeys
- Physical Wireless switch
- SD card slot: Linux outputs an "irq 18: nobody cared" message when
inserting a card, after which it disables the IRQ
Unknown/untested:
- Dock
- Smartcard (slot and contactless)
- Firewire
- eSATA
- TPM
- Battery (my battery is at the end of its lifespan)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Removing default on/off from mainboard devicetrees is left as a follow-up.
Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.
The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.
Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These files are no longer required by the build system.
Change-Id: I327e7c9211f46d4694591abab11cb38c9180bddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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These files contain no creative content, and therefore have no
copyright. This effectively means that they are in the public
domain.
This commit updates the unlicensable empty (and effectively empty)
files with the CC-PDDX identifier for license compliance scanning.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only
mainboard using the SCH5545 code, `dell/snb_ivb_workstations`.
Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The Dell OptiPlex 9010 uses a Q77 PCH, which is Panther Point. The only
difference is the definition of the `CROS_GPIO_DEVICE_NAME` macro, which
is not used for non-ChromeOS coreboot builds.
Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2.
Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Precision is a Mid Tower chassis platform with very similar mainboard
to OptiPlex 9010. It has one more PCIe port and a PCI port. It also
incorporates C216 chipset instead of Q77 and enables DRAM ECC support.
Other changes are related to subsystem ID and fan control
initialization.
TEST=Boot Dell Precision T1650 and launch Debian 10.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Fix the HWM sequence matching to the chassis. HWM sequence for SFF
was incorrectly passed to MT chassis HWM initialization.
Vendor code also applies a fix-up for MT/DT chassis. This fixup was
missing one register read compared to the vendor code. Add the missing
read and guard the fixup depening on the returned value to match the
vendor code behavior. Not doing so resulted in increased fan speeds
on Dell Precision T1650 compared to Dell's firmware.
TEST=Boot Dell Precision T1650 and hear the fans are as silent as on
Dell's firmware
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Discovered this chassis identification number on Dell Precision
T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid
Tower (MT) chassis.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3487b0ab94e565862ed727e9a91bd1efb364d43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
1) If _PRS is present, must have _CRS and _SRS
2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
4) If _SRS is present, probably should have a _DIS (Remark only)
IASL will issue a warning for each missing dependency.
Ignore this warnings for existing ASL code and issue a message when the build is complete.
Change-Id: I28b437194f08232727623009372327fec15215dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Dumped using inteltool from the Dell BIOS version A30.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCI_EXP_EN, PME_EN and PME_B0_EN GPEs used for PCI devices.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If unspecified, chipset code already uses 101, and 0x65 == 101.
Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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These boards have a socketed CPU, and the PCI device ID for the iGPU
depends on the installed CPU. Specifying a default doesn't make sense.
Change-Id: Iee6749e4fb691f09664cc6ffb3cbf66e4230fa9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54361
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most boards use `device domain 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The `tcrt` and `tpsv` values in GNVS can be used to implement thermal
management in ACPI. However, not all mainboards use these values.
On mainboards where `tcrt` and `tpsv` are not used in ACPI tables and
are the only values set in the `mainboard_fill_gnvs` function, remove
them as well as the entire `acpi_tables.c` file. Most files come from
autoport, which unconditionally generates this file.
Change-Id: If2315ddd9700e2da0a24ffecc20acb5c1a1d688e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Always print the chosen fan mode, not only when get_int_option() returns
the fallback value. Callers of get_int_option() should not try to handle
option-related errors, and simply proceed using the fallback value.
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
Change-Id: Ic8adbe557b48a46f785d82fddb16383678705e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4d949d252ca24ebd4e4ed9c7dd17ede3810a8bfd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop unused sandybridge.h includes to avoid build failures on Ironlake.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unify the debug messages on raised SMIs.
Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
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Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They aren't specific to AC power operation anymore. Also adapt autoport.
Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All mainboards use the same values for AC and battery, even desktop
boards without a battery. Use the AC values everywhere and drop the
battery values. Subsequent commits will rename the AC power options
accordingly, and will also clean up the corresponding acpigen code.
This is intentional so as to ease reviewing the devicetree changes.
Also update util/autoport accordingly.
Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Coverity detects uninitialized variables through PASS_BY_REFERENCE
usage. Fix this issue by initializing variables before their uage.
Found-by: Coverity CID 1429765, 1429772, 1429780
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie583b072a76949fb3f17c1271a6427ee942db0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I3d0ca401cf5268962bcd9074f94c37724cc0a836
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Lenovo ThinkPad X230
- Dell OptiPlex 9010
- Roda RW11 (with MRC raminit)
Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<'
Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New kconfig dislikes unquoted slashes.
Change-Id: Ief242de081071021b9c904a24535d025f6674270
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also update autoport accordingly.
Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's almost 10 years old. It never worked. It's a soldered in FLASH,
so mistakes are fatal. It's got no redeeming features.
Remove the dell directory. In 12 years of trying to work with Dell
we have not had much interest. It's misleading to have it there.
Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b
Reviewed-on: http://review.coreboot.org/876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We used several names for that same value, and hardcoded the value
at some more places.
They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).
Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.
Coccinelle script:
@@
identifier mc;
@@
(
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
|
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
)
Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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As stated in some code files, fixup_virtual_wire was established
to avoid touching 200 invocations of the mptable code.
Let Coccinelle do it:
@@
type T;
identifier v;
@@
-void fixup_virtual_wire(T v)
-{ ... }
@@
expression A;
identifier v;
@@
-v = smp_write_floating_table(A);
+v = smp_write_floating_table(A, 0);
@@
expression A;
identifier v;
@@
-v = smp_write_floating_table(A, 0);
-fixup_virtual_wire(v);
+v = smp_write_floating_table(A, 1);
Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/245
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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all boards to the new config scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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We currently use "COREBOOT" unconditionally as the "OEM ID" in our
mptable.c files, and hardcode the mainboard name in mptable.c like this:
mptable_init(mc, "DK8-HTX ", LAPIC_ADDR);
However, the spec says
"OEM ID: A string that identifies the manufacturer of the system hardware."
(Table 4-2, page 42)
so "COREBOOT" doesn't match the spec, we should use the hardware vendor name.
Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID"
(truncate/fill it to 8 characters as per spec).
Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID",
and truncate/fill it to 12 characters as per spec, if needed.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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src/arch/x86.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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