diff options
| author | Keith Hui <buurin@gmail.com> | 2023-11-11 17:25:48 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-26 11:08:14 +0000 |
| commit | b4f47e8067a7ef55ad5e2f18058031a871edbfef (patch) | |
| tree | 1a6046ce808e6a03070a66efcf125cbc74b8cb17 /src/mainboard/dell | |
| parent | e9ed7928cf31312629b30acd6a1788a64f547baf (diff) | |
nb/intel/haswell: Move SPD addresses to devicetree
Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/dell')
| -rw-r--r-- | src/mainboard/dell/e7240/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/dell/e7240/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/dell/optiplex_9020/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/dell/optiplex_9020/romstage.c | 9 |
4 files changed, 2 insertions, 16 deletions
diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb index c408383c70..ee5f1ab545 100644 --- a/src/mainboard/dell/e7240/devicetree.cb +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/e7240/romstage.c index 6b2cb7a80c..c439bfcf15 100644 --- a/src/mainboard/dell/e7240/romstage.c +++ b/src/mainboard/dell/e7240/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -17,12 +16,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb index 841285bb9c..223831cd87 100644 --- a/src/mainboard/dell/optiplex_9020/devicetree.cb +++ b/src/mainboard/dell/optiplex_9020/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell # This mainboard has VGA register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c index 8198eb0503..b9aae99d4c 100644 --- a/src/mainboard/dell/optiplex_9020/romstage.c +++ b/src/mainboard/dell/optiplex_9020/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -15,14 +14,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, |