coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-16	soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config	Subrata Banik
2021-09-17	skylake DDR4 boards: Set `CaVrefConfig` to 2	Angel Pons
2021-08-28	soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default	Felix Singer
2021-05-14	mb/clevo/n130wu: Use device alias names in devicetree	Felix Singer
2021-04-19	mb/clevo/kbl-u: Move memory init config to variant level	Felix Singer
2021-04-12	mb/*: drop LPC generic range for port 80	Michael Niewöhner
2021-01-01	nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings	Michael Niewöhner
2020-12-29	mb/clevo/n13xwu: Disable GMM PCI device	Felix Singer
2020-12-29	mb/clevo/n130xu: Remove disabled devices from devicetree	Felix Singer
2020-12-21	Revert "mb/clevo/kbl-u: drop duplicated configuration of UART pads"	Felix Singer
2020-12-20	mb/clevo/kbl-u: drop duplicated configuration of UART pads	Michael Niewöhner
2020-12-08	mb/*: Remove SATA_AHCI config from SKL/KBL based devicetrees	Felix Singer
2020-12-08	soc/intel/skylake: Shorten SATA mode enum value names	Felix Singer
2020-12-06	mb/clevo/kbl-u: Add a seperate method for early GPIOs	Felix Singer
2020-12-06	mb/clevo/kbl-u: Move mainboard/gpio.h to variant/gpio.h	Felix Singer
2020-11-20	mb/clevo/kbl-u: Add Clevo N130WU/N131WU	Felix Singer