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path: root/src/mainboard/asus/p8x7x-series/variants
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2024-02-12mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pinsKeith Hui
Goal is to use existing defines for all pins to make the file self-documenting, but it would make lines too long, so I'll just start with the NC pins. TEST=Timeless binary did not change. Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79733 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/asus/p8x7x-series: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27mb/asus/p8z77-m_pro: Drop useless early init codeKeith Hui
Drop code that puts Super I/O into config mode, select serial device, then leave config mode right away having done nothing. I'll also take this chance to revise its #includes based on include-what-you-use results. Change-Id: I304fc1610740375b59121b6b8784122440795838 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73693 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/asus/p8z77-m: Ensure RAM stays powered in ACPI S3 suspendKeith Hui
Enable 3VSBSW# in NCT6779D super I/O like other variants in the family, needed to maintain power to memory during S3 suspend. Without it resuming totally fails. (Enabling it in devicetree is OK; it needs not be done in early board init.) TEST=Resuming from S3 works. Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/*: Update SPD mapping for sandybridge boardsKeith Hui
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-25SNB+MRC boards: Migrate MRC settings to devicetreeKeith Hui
For Sandy Bridge boards with MRC raminit support, migrate as much MRC settings to devicetree as possible, to stop mainboard code from needlessly overwriting entire PEI data structure, so they will not interfere with upcoming transition to one standard Haswell way of providing SPD info to northbridge. Some exceptions allowed are described below and in code comments. SPD-related items are kept out of devicetree for now. They will be migrated (with a different representation) with the Haswell SPD transition. google/{butterfly,link,parrot,stout} have max DDR3 frequency set in pei_data to 1600 (2*800), but in devicetree to 666. The reason for the difference seems to be problems with native raminit code. These are converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an added "fix me" tag. asus/p8x7x-series also needs the same treatment, based on testing various memory on p8z77-m hardware. TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested. Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-12mb/asus/p8z77-m: Make onboard NIC a child device below PCIe port 5Fabian Groffen
The Realtek RTL8111F NIC is currently not defined at all, nor as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as it's appropriate for on-board ethernet devices. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/asus/p8z77-m: Add TPM configFabian Groffen
This board has a TPM connector, enable support for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-03-23nb/intel/snb: Abolish mainboard_should_reset_usb()Keith Hui
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25mainboard/asus/p8x7x-series: Add new variant P8Z77-MKeith Hui
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps. Working: - Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows Not working: - PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot Untested: - PS/2 keyboard - Internal USB3 ports - Digital audio out Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-06mb/**/gma-mainboard.ads: Use lowercase for `others`Angel Pons
These two files are the only places where the `others` keyword is capitalised. Use lowercase for consistency with the rest of the tree. Change-Id: I6b785e28d1d00a11b802a44348a7132ceb6b599d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57399 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/asus: Rename p8z77-series to p8x7x-seriesBill XIE
Many more asus boards using Panther Point PCH other than Z77 can be added as variants of this series. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I3e0b5734658912a69ccde94d530399059502c4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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