mainboard/asus/p8x7x-series: Add new variant P8Z77-M

Constructed out of a mix of autoport results, p8z77-m_pro, and
tool dumps.

Working:

- Core i7-3770K CPU
- SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903
  (all further tests are under these versions)
- USB2 / USB3
- SATA
- Gigabit ethernet
- CPU temp sensors (memtest86+ 5.0.1)
- Hardware monitoring under Linux
- Native and MRC raminit
- PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600)
- Integrated graphics with Intel OpROM and libgfxinit (all ports)
- Serial port
- Windows with libgfxinit framebuffer
- 2ch sound playback, Linux and Windows

Not working:

- PS/2 mouse
- 6ch analog audio out
- PCI POST card in PCI slot

Untested:

- PS/2 keyboard
- Internal USB3 ports
- Digital audio out

Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

9 files changed, 577 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt
new file mode 100644
index 0000000000..96774748a7
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P8Z77M/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default
new file mode 100644
index 0000000000..3cc854d6c3
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Disable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored otherwise
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
new file mode 100644
index 0000000000..3053b8d913
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
@@ -0,0 +1,136 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0            120     r       0        reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       3        boot_option
+388          4       h       0        reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395          4       e       4        debug_level
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408          1       e       1        nmi
+
+409          2       e       5        power_on_after_fail
+411          2       e       6        sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416          5       e       7        gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421          2       e       8        usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423          1       e       1        usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424          1       e       1        usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464          32      r       0        mrc_scrambler_seed
+496          32      r       0        mrc_scrambler_seed_s3
+528          16      r       0        mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544          16      h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value   text
+
+# Generic on/off enum
+1     0     Disable
+1     1     Enable
+
+# boot_option
+3     0     Fallback
+3     1     Normal
+
+# debug_level
+4     0     Emergency
+4     1     Alert
+4     2     Critical
+4     3     Error
+4     4     Warning
+4     5     Notice
+4     6     Info
+4     7     Debug
+4     8     Spew
+
+# power_on_after_fail
+5     0     Disable
+5     1     Enable
+5     2     Keep
+
+# sata_mode
+6     0     AHCI
+6     1     Compatible
+6     2     Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7     0     32M
+7     1     64M
+7     2     96M
+7     3     128M
+7     4     160M
+7     5     192M
+7     6     224M
+7     7     256M
+7     8     288M
+7     9     320M
+7     10    352M
+7     11    384M
+7     12    416M
+7     13    448M
+7     14    480M
+7     15    512M
+7     16    1024M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+#        xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+#             and the computer is reset, keep the USB 3.0 mode.
+#
+8     0     Disable
+8     1     Enable
+8     2     Auto
+8     3     SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+#     <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt
new file mode 100644
index 0000000000..26ab42def2
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
new file mode 100644
index 0000000000..dfcdd231ef
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	/* {enable, current, oc_pin} */
+	{1, 2, 0}, /* Port 0: USB3 front internal header, top */
+	{1, 2, 0}, /* Port 1: USB3 front internal header, bottom */
+	{1, 2, 1}, /* Port 2: USB3 rear, top */
+	{1, 2, 1}, /* Port 3: USB3 rear, bottom */
+	{1, 2, 2}, /* Port 4: USB2 rear, PS2 top */
+	{1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */
+	{1, 2, 3}, /* Port 6: USB2 rear, ETH, top */
+	{1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */
+	{1, 2, 4}, /* Port 8: USB2 internal header USB910, top */
+	{1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */
+	{1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */
+	{1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */
+	{1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */
+	{1, 2, 6}  /* Port 13: USB2 internal header USB1314, bottom */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	/*
+	 * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O
+	 * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083
+	 * bridge to this port, to receive POST codes.
+	 */
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+	return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei)
+{
+	uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
+	uint16_t usbcfg[16][3] = {
+		/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
+		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
+		{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
+	};
+
+	memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr));
+
+	pei->gbe_enable = 0;	   /* Board uses no Intel GbE but a RTL8111F */
+	pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */
+
+	memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg));
+
+	/* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */
+	pei->ddr3lv_support = 1;
+	/*
+	 * PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+	 * but might cause some system instability!
+	 */
+	pei->pcie_init = 1;
+	/*
+	 * 4 bit switch mask. 0=not switchable, 1=switchable
+	 * Means once it's loaded the OS, it can swap ports
+	 * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+	 */
+	pei->usb3.hs_port_switch_mask = 0xf;
+	/*
+	 * USB 3 mode settings.
+	 * These are obtained from option table then bit masked to keep within range.
+	 */
+	/*
+	 * 0 = Disable: work always as USB 2.0(ehci)
+	 * 1 = Enable: work always as USB 3.0(xhci)
+	 * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+	 * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+	 *     and reboots, it will keep the USB3.0 speed
+	 */
+	pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3;
+	/* 1=Load xHCI pre-OS drv */
+	pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1;
+	/*
+	 * 0=Don't use xHCI streams for better compatibility
+	 * 1=use xHCI streams for better speed
+	 */
+	pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1;
+}
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads
new file mode 100644
index 0000000000..1bf8323f1b
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,	-- DVI-D port
+      HDMI3,	-- HDMI port
+      Analog,	-- VGA port
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c
new file mode 100644
index 0000000000..c1012e3f82
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
new file mode 100644
index 0000000000..5830331a7c
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+	0x104384a8, /* Subsystem ID */
+	15,         /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x104384a8),
+	AZALIA_PIN_CFG(0, 0x11, 0x90430130),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	0x80862806, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	4,          /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
new file mode 100644
index 0000000000..9659ed14a3
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -0,0 +1,81 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1043 0x84ca inherit
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			register "gen1_dec" = "0x000c0291"
+
+			device pci 1c.0 on  end	# PCIe Port #1 (PCIe x4 slot)
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 on  end	# PCIe Port #5 (PCIe x1 slot)
+			device pci 1c.5 on  end	# PCIe Port #6
+			device pci 1c.6 on  end	# PCIe Port #7 (PCI slot via ASM1083)
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1f.0 on # LPC bridge
+				chip superio/nuvoton/nct6779d
+					device pnp 2e.1 off end		# Parallel
+					device pnp 2e.2 on		# UART A
+						io 0x60 = 0x3f8		# COM1 address
+						irq 0x70 = 4
+					# Below are global config settings to replicate OEM
+						drq 0x26 = 0x10		# Before accessing CR10/11/13/14, CR26:4 must be set to 1
+						drq 0x13 = 0xff		# IRQs 0-15 active low
+						drq 0x14 = 0xff
+						drq 0x1a = 0x02
+						drq 0x1b = 0x60
+						drq 0x2c = 0x00		# GP27, 3VSBSW#, No TSI
+					end
+					device pnp 2e.3 off end		# UART B, IR
+					device pnp 2e.5 on		# PS2 KBC
+						io  0x60 = 0x0060	# KBC1 base
+						io  0x62 = 0x0064	# KBC2 base
+						irq 0x70 = 1		# Keyboard IRQ
+						irq 0x72 = 12		# Mouse IRQ
+						drq 0xf0 = 0x82		# KBC 12Mhz/A20 speed/sw KBRST
+						drq 0x2a = 0x48		# UART A, PS/2 mouse, PS/2 keyboard
+						drq 0x22 = 0xd7		# Power down UART B and LPT
+					end
+					device pnp 2e.6 off end		# CIR
+					device pnp 2e.8 on		# WDT1
+						drq 0xe0 = 0x7f		# GP07 output
+						drq 0xe1 = 0x80		# GP07 high
+					end
+					device pnp 2e.a on		# ACPI
+						drq 0xe7 = 0x11		# HWM reset by LRESET#, 0.5s S3 delay for compatibility
+						drq 0xf2 = 0x5d		# Enable RSTOUT[0-2]# and PME
+					end
+					device pnp 2e.b on		# HWM, front panel LED
+						io 0x60 = 0x290		# HWM address
+						io 0x62 = 0		# SB-TSI address (not used)
+						drq 0xe4 = 0xf9		# GP50, GP52, PWROK#
+						drq 0xf0 = 0x3e		# Enable all fan input debouncers
+					end
+					device pnp 2e.e off end		# CIR wake-up
+					device pnp 2e.f on		# GPIO PP/OD select
+						drq 0xe4 = 0xfc		# GP50,GP51 PP
+						drq 0xe6 = 0x7f		# GP7x OD
+					end
+					device pnp 2e.9 off end		# GPIO 8
+					device pnp 2e.308 on end	# GPIO by I/O
+					device pnp 2e.108 on end	# GPIO 0
+					device pnp 2e.109 on end	# GPIO 1
+					device pnp 2e.209 on		# GPIO 2
+						drq 0xe0 = 0xbf		# GP26 output
+						drq 0xe1 = 0xc0		# GP26 high
+					end
+					device pnp 2e.309 off end	# GPIO 3
+					device pnp 2e.409 off end	# GPIO 4
+					device pnp 2e.509 on		# GPIO 5
+						drq 0xf4 = 0xfc		# GP50,GP51 output
+						drq 0xf5 = 0xc4		# GP50,GP51 low
+					end
+					device pnp 2e.609 off end	# GPIO 6
+					device pnp 2e.709 off end	# GPIO 7
+				end
+			end
+		end
+	end
+end