coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
2019-10-11	sb/intel/i82801gx: Move CIR init to a common place	Arthur Heymans
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-18	cpu/intel: Enter romstage without BIST	Kyösti Mälkki
2019-07-18	mb///gpio: Use static for const structures	Peter Lemenkov
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-05-15	src/mainboard: Remove unneeded include <arch/io.h>	Elyes HAOUAS
2019-05-06	src: Remove unused include <halt.h>	Elyes HAOUAS
2019-04-29	src/mb: Use system_reset()	Elyes HAOUAS
2019-04-13	sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	Patrick Rudolph
2019-03-13	{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	device/pnp: Add header files for PNP ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-08	mb/{asrock,intel,kontron}: Include missing <arch/io.h>	Elyes HAOUAS
2019-02-07	src: Remove unused include device/pnp_def.h	Elyes HAOUAS
2019-01-14	mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant	Angel Pons
2019-01-10	mb: Move timestamp_add_now to northbridge x4x	Elyes HAOUAS
2019-01-09	cpu/intel: Use the common code to initialize the romstage timestamps	Arthur Heymans
2019-01-08	sb/intel/i82801gx: Autodisable functions based on devicetree	Arthur Heymans
2019-01-07	src/mb/asus/p5qpl-am/romstage.c: Fix comment	Angel Pons
2018-12-28	arch/x86: Drop spurious arch/stages.h includes	Kyösti Mälkki
2018-12-24	mb/asus/p5qpl-am: Add mainboard	Arthur Heymans