coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-05	nb/intel/x4x: Remove apic 0 from devicetree	Arthur Heymans
2022-12-05	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	Arthur Heymans
2022-12-01	nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree	Arthur Heymans
2021-06-25	mb/asus/p5q_se: Add initial support	Alice Sell
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-10	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-04-10	src/mb: Remove unneeded spaces before/after tabs	Elyes HAOUAS
2020-04-06	mainboard/asus: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2020-01-21	mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)	Ivan Vatlin
2020-01-10	mb/asus/p5qc/devicetree.cb: Drop zero values	Angel Pons
2020-01-10	mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixes	Angel Pons
2019-11-12	sb/intel/i82801jx: Add common code for LPC decode	Arthur Heymans
2019-03-25	mb/asus/{p5qc,p5q_pro}: Correct mapping of PCI-E 1x ports	Bill XIE
2018-11-18	mb/asus/p5qc: Add p5ql_pro mainboard as variant	Angel Pons
2018-11-05	mb/asus/p5qc: Fix spelling of Marvell	Jonathan Neuschäfer
2018-11-04	src/mb/asus/p5qc: Fix some mistakes	Angel Pons
2018-10-15	mb/asus/p5q_pro: Add mainboard	Arthur Heymans