| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-12-05 | nb/intel/x4x: Remove apic 0 from devicetree | Arthur Heymans |
| 2022-12-05 | cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm | Arthur Heymans |
| 2022-12-01 | nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree | Arthur Heymans |
| 2021-06-25 | mb/asus/p5q_se: Add initial support | Alice Sell |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |