| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-12 | sb/intel/i82801gx: Add common LPC decode code | Arthur Heymans |
| 2019-07-20 | mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode` | Nico Huber |
| 2019-06-06 | sb/intel/i82801gx: Detect if the southbridge supports AHCI | Arthur Heymans |
| 2019-06-05 | mb/*/devicetree.cb: Remove unavailable PCIe ports | Arthur Heymans |
| 2018-11-12 | mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 | Arthur Heymans |
| 2017-07-12 | mb/asus/p5gc-mx: Implement resume from S3 support | Arthur Heymans |
| 2016-12-28 | mb/asus/p5gc-mx: Fix and complete SIO devicetree options | Arthur Heymans |
| 2016-12-22 | mb/asus/p5gc-mx: Add mainboard | Arthur Heymans |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |